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LMK04832: Help getting synchronized clock outputs in multi-LMK04832 setup

Nick Pillitteri
Prodigy 30 points
Part Number: LMK04832

Hi,

I have a multi-LMK04832 setup where each LMK is taking in the same 6MHz clock as its reference clock (matched cables, etc) and has a 100MHz external VCXO. It is creating the following clocks:

  • 6MHz clocks (including SYSREF)
  • 132 MHz clocks

I am running the clocks in nested 0-delay mode. I am attaching my register values

HexRegisterValues_xrf16_lmk04832_extref_6MHz.txt
Fullscreen
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
R0 (INIT) 0x000090
R0 0x000010
R2 0x000200
R3 0x000306
R4 0x000463
R5 0x0005D1
R6 0x000670
R12 0x000C51
R13 0x000D04
R256 0x010018
R257 0x01010A
R258 0x010280
R259 0x010340
R260 0x010410
R261 0x010500
R262 0x010601
R263 0x010700
R264 0x010818
R265 0x01090A
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

I have the ability to see CLKOUT3 on the multiple LMK04832s, so I can set that output to be either 6MHz or 132MHz. When I set it to 132MHz, I am noticing that the 132MHz clocks do not always come up synchronously (or even at predictable phase offsets which I could work with) between the LMKs. They are coming up at the correct frequencies.

I have tried doing the "SYNC Dividers" sync that the GUI does with the same register writes and this is not aligning the phases either.

What am I missing? I am able to provide a matched SYNC pulse to the input pins of the LMKs from an FPGA if needed but the documentation seems conflicting over whether this needs to be done or not (and what the necessary pre/post register writes would be).

Please advise. Thank you.

  • 0
    TI__Mastermind 31900 points

    Nick,

    Since you have the 6MHz from the SYSREF divider fed back into PLL1, you're 95% of the way there. You just need to re-clock your SYNC edges to the SYSREF divider.

    Your SYNC procedure should look like:

    1. Start with all relevant device clock DDLY_PD cleared and all DDLYs set to equal values
    2. Set SYSREF_MUX to re-clocked
    3. Clear SYNC_DISx on all relevant clock outputs (not necessary for SYNC_DISSYSREF since this is in ZDM feedback)
    4. Toggle SYNC pin, or just set/clear SYNC_POL bit (timing irrelevant, pulse just needs to be longer than one complete 6MHz clock cycle)
    5. Set SYNC_DISx again on all clock outputs
    6. Restore SYSREF_MUX to your desired usage mode

    Regards,

    Derek Payne

  • +1 in reply to Derek Payne
    Prodigy 30 points

    Thanks Derek. I think the only thing I was doing different was using normal sync instead of reclocked sync and clearing SYNC_DISSYSREF, but things seem better now. I'll report back if any issues.

    Thanks again!