Hi,
I have a multi-LMK04832 setup where each LMK is taking in the same 6MHz clock as its reference clock (matched cables, etc) and has a 100MHz external VCXO. It is creating the following clocks:
- 6MHz clocks (including SYSREF)
- 132 MHz clocks
I am running the clocks in nested 0-delay mode. I am attaching my register values
R0 (INIT) 0x000090 R0 0x000010 R2 0x000200 R3 0x000306 R4 0x000463 R5 0x0005D1 R6 0x000670 R12 0x000C51 R13 0x000D04 R256 0x010018 R257 0x01010A R258 0x010280 R259 0x010340 R260 0x010410 R261 0x010500 R262 0x010601 R263 0x010700 R264 0x010818 R265 0x01090A R266 0x010A00 R267 0x010B40 R268 0x010C10 R269 0x010D00 R270 0x010E01 R271 0x010F10 R272 0x011018 R273 0x01110A R274 0x011280 R275 0x011340 R276 0x011410 R277 0x011500 R278 0x011601 R279 0x011700 R280 0x011818 R281 0x01190A R282 0x011A00 R283 0x011B40 R284 0x011C20 R285 0x011D00 R286 0x011E01 R287 0x011F10 R288 0x012018 R289 0x01210A R290 0x012200 R291 0x012340 R292 0x012410 R293 0x012500 R294 0x012601 R295 0x012701 R296 0x012818 R297 0x01290A R298 0x012A00 R299 0x012B40 R300 0x012C10 R301 0x012D00 R302 0x012E01 R303 0x012F01 R304 0x013018 R305 0x01310A R306 0x013200 R307 0x013340 R308 0x013420 R309 0x013500 R310 0x013601 R311 0x013711 R312 0x013825 R313 0x013903 R314 0x013A02 R315 0x013B10 R316 0x013C00 R317 0x013D08 R318 0x013E01 R319 0x013F0D R320 0x014000 R321 0x014100 R322 0x014200 R323 0x014311 R324 0x0144FF R325 0x014510 R326 0x014618 R327 0x01471A R328 0x014802 R329 0x014942 R330 0x014A02 R331 0x014B06 R332 0x014C00 R333 0x014D00 R334 0x014EC0 R335 0x014F7F R336 0x015000 R337 0x015102 R338 0x015200 R339 0x015300 R340 0x015405 R341 0x015500 R342 0x015601 R343 0x015700 R344 0x01580A R345 0x015900 R346 0x015A01 R347 0x015BD4 R348 0x015C20 R349 0x015D00 R350 0x015E1E R351 0x015F1B R352 0x016000 R353 0x016119 R354 0x01624D R355 0x016300 R356 0x016400 R357 0x01650C R361 0x016958 R362 0x016A20 R363 0x016B00 R364 0x016C00 R365 0x016D00 R366 0x016E3B R371 0x017310 R375 0x017700 R386 0x018200 R387 0x018300 R358 0x016600 R359 0x016700 R360 0x0168C6 R1365 0x055500
I have the ability to see CLKOUT3 on the multiple LMK04832s, so I can set that output to be either 6MHz or 132MHz. When I set it to 132MHz, I am noticing that the 132MHz clocks do not always come up synchronously (or even at predictable phase offsets which I could work with) between the LMKs. They are coming up at the correct frequencies.
I have tried doing the "SYNC Dividers" sync that the GUI does with the same register writes and this is not aligning the phases either.
What am I missing? I am able to provide a matched SYNC pulse to the input pins of the LMKs from an FPGA if needed but the documentation seems conflicting over whether this needs to be done or not (and what the necessary pre/post register writes would be).
Please advise. Thank you.
