Hi Tina,

What is the ppm accuracy of your XO?

I will check your config on Monday to see if I also face similar issues. From your explanation, I don't see an error in your step yet.

Can you also connect STATUS0 and STATUS1 to a scope with these register settings, then share what you see?

Regards,

Jennifer

Hi , Jennifer

Thanks for your reply .

My XO is ECS-TXO-2520MV-120-AY-TR . It is 2.5ppm and 12MHZ .

I change STATUS0 and STATUS1 settings as what you say , then write to the LMK05318B . 

I see STATUS0 is high and STATUS1 is low .

Regards

Tina

Hi Tina,

The STATUS0 and STATUS1 settings I shared are not logic high/low signals, they are waveforms that represent the PRIREF (DPLL R divider) and the VCO output feedback (DPLL FB divider).

Can you please share a scope shot of these two registers? 

Regards,

Jennifer

Hi , Jennifer

STATUS0 is always high and STATUS1 is low .

I made a mistake ： When  I read register R411: 0x8 , I think PRIREF is valid .But it means SECREF valid . So PRIREF is not valid 

I get this topic that is similar to my problem .

I read registers R13, R14 and R411 to get the following:

R13: 0x08
R14: 0xC0
R411: 0x08

Could you please check my tcs files again .LMK05318BRGZT_GPS_1HZ_NEO-M8N_XO12MHZ_2p5PPS_50MHZ_1024.tcs

Regards

Tina

Hi Tina,

I can provide an update tomorrow, 10/25,

Regards,

Jennifer

Tina,

Sorry for the delay, I did not get around to testing the configuration today; I will work on it tomorrow.

Regards,

Jennifer

Hi , Jennifer

I'm waiting for your updata .

This is a big problem for my project and I have to solve it.

Please ，Please help me.

Regards

Tina

Hi Tina,

I have been facing issues getting the 1-PPS setup on my bench. In the meantime, can you please test with this configuration? Make sure to issue a soft reset after loading the settings.

e2e_XO=12 MHz_REF=1PPS.tcs

Please let me know if these signals get set: PRIREF_VALSTAT, LOPL_DPLL, LOFL_DPLL. It can take several minutes to an hour for LOPL_DPLL to clear.

Regards,

Jennifer

Hi , Jennifer

I am extremely grateful  for your reply .

I use your tcs settings ,. PRIREF_VALSTAT  is  0  ;  LOPL_DPLL, LOFL_DPLL are 1 .

Why 1pps cant be validate?

I did a test . I use a signal generator to generate 1MHz clk for PRIREF 。

Several minutes later , PRIREF_VALSTAT is 1 ;  LOFL_DPLL  is 0 ; LOPL_DPLL is still 1 .

I think this situation is normal . LOPL_DPLL needs time to clear .

Regards

Tina

Hi Tina,

Can you please share a scope shot of the 1-PPS PRIREF input?

Regards,

Jennifer

Hi , Jennifer

Sorry for the delay.

Regards

Tina

Hi Tina,

How wide (in seconds) is the 1-PPS pulse high?

Regards,

Jennifer

Hi , Jennifer

The duty cycle is 10%.

Regards

Tina

Hi , Jennifer

Do you have any other suggestions?

Is there a problem with the 1-PPS?

Regards

Tina

Hi , Jennifer

Please let me know if you need any more information.

Do you have any other suggestions?

Regards

Tina

Hi Tina,

Sorry for the delay! I still have not been able to setup my bench to do more testing on your script. Can you try these things:

1. Poll for the PRIREFVAL_STAT signal with 1-PPS to the PRIREF pin. I want to see if at any point it does get set.
2. Is it possible to increase the pulse width of the 1-PPS (try 50%)? I want to make sure this isn't the issue. 

Regards,

Jennifer

Hi , Jennifer

ok , I will try to control the pulse width of the 1-PPS . 

If there are any new discoveries, I will let you know.

Regards

Tina

Hi , Jennifer

The 50% pulse width of the 1-PPS does not work .

PRIREF_VALSTAT  is  always  0 .

Only when I turn off  1-pps phase detector ，PRIREF_VALSTAT can be 1 。

I have test the PPS ， The phase shift of PPS is only a few tens of ns.

Do you have any other suggestions?

Regards

Tina

Tina,

The team is currently out for the Thanksgiving holiday. Please expect a response by Monday (PST) for any further queries.

Thanks,

Kadeem

Hi，Kadeem

Thanksgiving wishes for you , your team and your family .

Regards

Tina

Hi , Jennifer

I set the signal pulse width to 50% ，  but I dont know if this is the reason for not locking.

 I tried 1MHZ /20HZ /1HZ 。Only when I turn off window detector  or 1-pps phase detector ，DPLL can be locked。

The difference is in terms of time. 1HZ takes a few hours.

Is this locking effective? Is the output clock locked with 1PPS? 

Regards

Tina

Hi Tina,

The other thought I have is the XO source. We have seen XO inputs with high wander have issues locking. I don't see concern with a frequency of 12 MHz and an accuracy of 2.5 ppm; however, it could be that it has high wander. Would you be able to capture a TIE plot of your XO? Are you able to test with a different source such as a clean signal generator (which likely has an internal OCXO)?

Regards,

Jennifer