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LMK05318B: 1PPS Default Configuration Loss of Lock

Part Number: LMK05318B

Hi,

my problem is similar to this topic. I succesfully generate 125 MHz and 1 Hz outputs, but I cant get lock (i suppouse that chip is in free-run). R14 register status have LOFL, LOPL and HLDOVR flags. Register R13 is clear. I have Tics Pro from january 7 2022, i tried to use fix from this topic with same result.

Please let me know if you need any more information.

Can you help us understand why it would not be locking and what can be done to resolve this?

3757.HexRegisterValues.txt
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2
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5
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9
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12
13
14
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R0 0x000010
R1 0x00010B
R2 0x000235
R3 0x000332
R4 0x000404
R5 0x00050E
R6 0x000617
R7 0x00078E
R8 0x000802
R10 0x000AC8
R11 0x000B00
R12 0x000C1B
R13 0x000D08
R14 0x000E00
R15 0x000F00
R16 0x001000
R17 0x00111D
R18 0x0012FF
R19 0x001308
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Q100_max.tcs

  • Hello, 

    I'm seeing R14 (DPLL lock status) reading 0h meaning lock, this is both in the raw registers and .tcs file you shared. So what exactly is the issue? 

    Regards,

    Amin 

  • Hi,

    i attach configuration file generated from Tics pro. When i read device register from running hardware i have this : 

    7077.regs.txt
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    14
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    R0 = 16
    R1 = 11
    R2 = 53
    R3 = 66
    R4 = 2
    R5 = 14
    R6 = 31
    R7 = 3
    R8 = 2
    R10 = 200
    R11 = 0
    R12 = 27
    R13 = 8
    R14 = 240
    R15 = 0
    R16 = 0
    R17 = 29
    R18 = 255
    R19 = 13
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • Hello Maksymilian,

    Apologies for the delay. I will be testing your configuration to determine the issue and will provide you an update by the end of Monday.

    Regards,

    Kia Rahbar

  • Hi,

    On this couple days when i observe registers i recognize that i always have LOPL and LOFL, but i never seen LOR (on live read R14 register and R20 interupt register - never clear it yet, just read). I double check 1PPS signal from GPS and from generator and im sure that its ok. Im trying to change phase or lost of signal, but never have LOR. It is posible that my device newer recognize reference signal?

  • Hello Maksymilian,

    Can you please inform me whether the PRIREF_VALSTAT and SECREF_VALSTAT are high or low? These two bits will determine whether your input reference is valid.

    Regards,

    Kia Rahbar

  • Hi Kia,

    both PRIREF_VALSTAT and SECREF_VALSTAT are low (R411 in reg map attached to my post)

  • Hello Maksymilian,

    Please enable the amplitude detector and set the amplitude detector to CMOS Slew Rate Detector Mode. For a 1PPS input, the amplitude detector must be configured in this fashion.

    Regards,

    Kia Rahbar

  • Hi Kia,

    still the same. I tried already increase validation timer and modify 1 PPS Phase detector and its still doesnt lock.

    My schematic hardware is simple and tested with other PLL from Silicon Labs:

    1 PPS signal on PRIREF_P pin :

    Status regs from running hardware:
    R14 = 240 (LOPL_DPLL, LOFL_DPLL, HIST, HLDOVR is high, the rest - low)
    R20 = 240 (same as R14, so i think that LOR never get high)
    R13 = 8 (LOL_PLL2 only - i dont use APLL2)
    R411 = 0 (PRIREF and SECREF are not valid)

    My configuration:

    My configuration file from TICS Pro:

    0844.HexRegisterValues.txt
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    R0 0x000010
    R1 0x00010B
    R2 0x000235
    R3 0x000332
    R4 0x000404
    R5 0x00050E
    R6 0x000617
    R7 0x00078E
    R8 0x000802
    R10 0x000AC8
    R11 0x000B00
    R12 0x000C1B
    R13 0x000D08
    R14 0x000E00
    R15 0x000F00
    R16 0x001000
    R17 0x00111D
    R18 0x0012FF
    R19 0x001308
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    1212.Q100_max.tcs

  • Hello Maksymilian,

    Apologies for the delay. I spoke with my team and we believe we have determined your issue.

    The cause for your issue is that your XO input must have a maximum ppm accuracy of 4.9 ppm when using a 1PPS reference and a XO frequency of 12.8 MHz. The maximum allowable ppm error of 4.9 ppm is calculated using the following equation: max XO ppm = 1PPS cntr value (shown below)/ XO frequency (in MHz) = 63/12.8 = 4.9 ppm

    If the ppm accuracy of the XO does not meet this requirement you will not be able to lock to the 1PPS input.

    Also please note that I was incorrect about enabling the amplitude detector control. Please disable this feature.

    Regards,

    Kia Rahbar

  • Hi Kia,

    we try to use other generator LINK and we multiple frequency x3 with this LINK (we use rigol dg5252 synchronized to external GPS earlier just for test). Now my configuration looks like:

    Still cant lock and no valid reference in R411. We check raw register setting and recognize that R46:

    is set to 0x11 (AC-Differential (external termination)) for both reference. I think that it should be CMOS or DC-differential, but i dont see option to change it in TICS Pro. Im not shure that i can change it raw without consecuences in other settings (when i change it in raw registers and try to change some other options in GUI TICS pro overwrite it everytime).

    We're figthing with this about 3 weeks and we really need to make this work. Our clients wont wait forever.

    [PS]

    We're already validate our generator and its much better that 1ppm ( device does not allow for a more accurate measurement). 1PPS phase detector fails all time - when we disable it R411 says that signal is valid but stil doesnt lock. Witch flag says that 1PPS phase detector is ok?

  • Hello Maksymilian,

    I have created a new configuration and tested it in our lab.

    Please follow these steps and your device should be locking properly:

    1. Load this tcs file into TICS Pro:

    Q100_max_TI_working.tcs

    2. Once the file has been loaded, press the soft-reset chip button shown below:

    3. Then, readback the status bits and everything should be locking properly as shown below in my setup:

    Please note it will take 10-60 seconds for the LOFL_DPLL to go low and may take a few to many minutes for the LOPL_DPLL to go low as it takes a significant amount of time for the device to lock to a small frequency such as a 1PPS signal.

    Regards,

    Kia Rahbar

  • Hi Kia,

    i load and program your configuration and its better now. PRIREF is valid (R411), chip switch to PRIREF (R20[3]), but stil cant lock (LOFL and LOPL flags - valid reference is working for 3 hours).

    When i load your file TICS Pro show error:

    There is a lof of non-exists register in TICS Pro . Can u send a proper device profile?

  • Hello Maksymilian,

    The profile is correct. I created the configuration using the internal version of the GUI, so there are extra register that are not required for your configuration. This is why it skips those registers. 

    Please try reloading the file I had sent, then press the soft-reset chip, and then perform a readback of the status registers numerous times for a couple minutes. If you do not see the LOFL and LOPL go low, then perform another soft-reset chip and perform more readbacks of the status register.

    From a profile standpoint there should be no more changes required. I have tested the configuration on multiple devices and on the external version of TICS Pro and have not seen any issues.

    Regards,

    Kia Rahbar

  • Hi Kia,

    thanks for helping, your configuration almost resolve my issue. To make this work i need to manually change reference type to CMOS (R46 to 0x88) DC-coupled (TICS Pro doesnt support this option). When i change it a able to lock in 3-5 minutes. But its a very dangerous issue witch this DPLL. When it start working while there is no valid reference (stable GPS fix) or reference becomes invalid (switch off 1PPS signal when GPS doesnt fix) after lock DPLL never lock again (wait 14h for LOPL flag, LOFL clear pretty fast). I need to perform soft reset to get lock. Its bad because 125 MHz is used for the rest of switch and i need to keep it not disturbed.

    Is there any other option to force re-lock without soft-reset?

    Is there a flag for valid history? How do i now that chip is in holdover after loose reference and have valid history to hold signal?

  • Hello Maksymilian,

    You're welcome!

    A possible reason for why you may not be able to relock is that there is a drift in the accuracy due to the tuning word history when the device is in holdover. Please try turning off the tuning word history as shown below and see if that solves your issue.

    Unfortunately, we do not have a flag for valid history.

    To determine if the device has entered holdover, the HLDOVR flag can be used. If the flag is high the device is in holdover. The register associated with this flag is R14[4].

    Regards,

    Kia Rahbar

  • Hi Kia,

    disable Tunning Word History doesnt solve my problem. Still cant relock. I try to get some delay to PPS signal after lock (even 3000 ns phase offset) and DPLL works fine (lost of lock and try to relock). Problem is only if there is lost of signal (even for a very short time). I see that device run in holdover mode, after it recognize a valid reference it clear HLDOVR flag and try to lock. Is there any interactive register to force relock without soft reset? For now device doesnt react for changing in SRAM (i use direct write by I2C) without soft-reset.

    Can u change my configuration for 19.440 MHz OCXO? Maybe it will be better (12.8 MHz is out of stock).

    3463.Q100_max.tcs

  • Hello Maksymilian,

    Unfortunately, the only way to force relock is with a soft reset.

    Yes, a 19.44 MHz OCXO will provide a greater ppm valid range (3.24 ppm (63/19.44)) than the 60 MHz XO input (1.05 ppm (63/60)), so it will be much easier for the device to relock to the 1PPS input.

    I would recommend making the changes on your end first since you have it operating correctly on the initial lock. Please follow these steps:

    1. Load the working configuration and get the 1PPS to lock.

    2. Navigate to the XO page and input the new 19.44 MHz XO frequency as shown below.

    3. Navigate to the set outputs page and click calculate frequency plan as shown below.

    4. Perform a soft-reset and readback the status bits to see if everything is locking properly. If it is, save the file and load it again to try your relock test again.

    I can make the update and test the configuration next week if you are not able to get it working on your end.

    Also another test you can perform is to increase the tuning word history count and delay. This will allow for the holdover frequency to be much more accurate when you are in holdover and will allow you to relock much easier.

    Regards,

    Kia Rahbar

  • Hi Kia,

    we do some test and we see that problem witch relock is only when we loose signal and switchover appears. We even try to make reference "messy" ( DPLL loose LOPL flag)  and we gave the correct signal again. if the switchover event does not occur DPLL can lock pretty fast. In this configuration auto-revertive doesnt work (need soft-reset anyway). Is there a posibility to fix DPLL on PRI_REF and block switchover? We try to set manual holdover on PRI_REF, but even when we choose first reference and disable second there is still switchover event while 1PPS signal get valid/invalid. We really need to make 125 MHz clock not disturbed and we want to hold 1PPS signal from DPLL if GPS loose lock. IF DPLL cant go from holdover to lock without host ingerations (soft-reset) it is not usable in our application (we wait 14h for lock and doesnt have it).

  • Hello Maksymilian,

    Is there a posibility to fix DPLL on PRI_REF and block switchover?

    By disabling the tuning word history, our goal was to mimic having the DPLL only lock to PRI_REF. Disabling the tuning word would act as if we were on initial startup every time the 1PPS becomes valid.

    Can you please provide me the ppm accuracy of the output before DPLL lock, during DPLL lock, and during holdover? Based on the holdover frequency, we can set the tuning word history to make the holdover frequency more accurate so that we can recover from holdover.

    Regards,

    Kia Rahbar

  • Hi Maksymilian,

    We haven't heard from you long time on this and assumed the issue got resolved. We are closing this thread and you feel free to reply on this or create new thread for further queries.

    Thanks!

    Regards,

    Ajeet Pal 

  • Hi Kia,

    we are running this DPLL now, we can lock in 3-5minuts (your configuration works very good), but sometimes DPLL wont try to synchronize APLL1 and stay in freerun (we can force him to rerun by disable and enable - R252[0]. The same operation we can do when we want to relock after loose reference). We see that DPLL synchronize APLL1 by Fraction N Divider (registers R110 - R114). At start he had 0x5555555555, DPLL change this value when it try to get lock, but sometimes he cant get action. Reference is valid and stable, uC get reset and initialize chip form 0. We can have software fix for that (if we see that he doesnt change it we can force him to). Have you a way to avoid this?

    Our start and load sequence is:
    Release reset pin and immediately put him in soft-reset state 
    Write all registers (R12 is still in soft-reset)
    Release soft reset and wait for lock

    Thanks!