LMK05318B: 1PPS Default Configuration Loss of Lock

Hello, 

I'm seeing R14 (DPLL lock status) reading 0h meaning lock, this is both in the raw registers and .tcs file you shared. So what exactly is the issue? 

Regards,

Amin 

Hi,

i attach configuration file generated from Tics pro. When i read device register from running hardware i have this : 

R0 = 16
R1 = 11
R2 = 53
R3 = 66
R4 = 2
R5 = 14
R6 = 31
R7 = 3
R8 = 2
R10 = 200
R11 = 0
R12 = 27
R13 = 8
R14 = 240
R15 = 0
R16 = 0
R17 = 29
R18 = 255
R19 = 13
R20 = 240
R21 = 1
R22 = 0
R23 = 85
R24 = 85
R25 = 0
R26 = 0
R27 = 0
R28 = 1
R29 = 19
R30 = 64
R32 = 68
R35 = 0
R36 = 3
R37 = 0
R38 = 0
R39 = 2
R40 = 3
R41 = 0
R42 = 1
R43 = 194
R44 = 1
R45 = 15
R46 = 17
R47 = 7
R48 = 80
R49 = 74
R50 = 30
R51 = 16
R52 = 16
R53 = 19
R54 = 0
R55 = 0
R56 = 15
R57 = 0
R58 = 15
R59 = 0
R60 = 15
R61 = 0
R62 = 99
R63 = 62
R64 = 149
R65 = 2
R66 = 248
R67 = 255
R68 = 8
R69 = 0
R70 = 0
R71 = 0
R72 = 33
R73 = 0
R74 = 0
R75 = 0
R76 = 0
R77 = 15
R78 = 0
R79 = 17
R80 = 128
R81 = 22
R82 = 0
R83 = 3
R84 = 132
R85 = 0
R86 = 0
R87 = 6
R88 = 26
R89 = 128
R90 = 0
R91 = 24
R92 = 0
R93 = 3
R94 = 132
R95 = 0
R96 = 0
R97 = 6
R98 = 26
R99 = 128
R100 = 41
R101 = 1
R102 = 34
R103 = 15
R104 = 31
R105 = 5
R106 = 0
R107 = 100
R108 = 0
R109 = 83
R110 = 85
R111 = 85
R112 = 85
R113 = 85
R114 = 85
R115 = 3
R116 = 1
R117 = 0
R118 = 0
R119 = 0
R120 = 0
R121 = 0
R122 = 0
R123 = 85
R124 = 85
R125 = 85
R126 = 85
R127 = 85
R128 = 0
R129 = 1
R130 = 0
R131 = 1
R132 = 1
R133 = 119
R134 = 0
R135 = 43
R136 = 0
R137 = 40
R138 = 229
R139 = 3
R140 = 2
R141 = 0
R142 = 1
R143 = 1
R144 = 119
R145 = 1
R146 = 137
R147 = 32
R149 = 13
R150 = 0
R151 = 1
R152 = 13
R153 = 41
R154 = 36
R155 = 136
R156 = 1
R157 = 0
R158 = 0
R159 = 0
R160 = 252
R161 = 6
R162 = 0
R164 = 0
R165 = 0
R167 = 0
R178 = 0
R180 = 0
R181 = 0
R182 = 0
R183 = 0
R184 = 0
R185 = 245
R186 = 1
R187 = 0
R188 = 0
R189 = 0
R190 = 0
R191 = 0
R192 = 240
R193 = 25
R194 = 25
R195 = 63
R196 = 255
R197 = 255
R198 = 63
R199 = 255
R200 = 255
R201 = 0
R202 = 63
R203 = 255
R204 = 255
R205 = 63
R206 = 255
R207 = 255
R208 = 0
R209 = 20
R210 = 0
R211 = 22
R212 = 0
R213 = 20
R214 = 0
R215 = 22
R216 = 0
R217 = 0
R218 = 0
R219 = 0
R220 = 1
R221 = 3
R222 = 147
R223 = 135
R224 = 0
R225 = 0
R226 = 0
R227 = 0
R228 = 1
R229 = 3
R230 = 147
R231 = 135
R232 = 0
R233 = 16
R234 = 16
R235 = 0
R236 = 195
R237 = 80
R238 = 0
R239 = 0
R240 = 195
R241 = 80
R242 = 0
R243 = 63
R244 = 63
R249 = 33
R250 = 0
R251 = 1
R252 = 109
R253 = 0
R254 = 0
R255 = 0
R256 = 0
R257 = 1
R258 = 0
R259 = 1
R260 = 2
R261 = 128
R262 = 1
R263 = 42
R264 = 5
R265 = 242
R266 = 0
R267 = 160
R268 = 4
R269 = 0
R270 = 3
R271 = 253
R272 = 31
R273 = 31
R274 = 31
R275 = 29
R276 = 29
R277 = 29
R278 = 0
R279 = 0
R280 = 0
R281 = 0
R282 = 0
R283 = 0
R284 = 30
R285 = 30
R286 = 0
R287 = 0
R288 = 0
R289 = 0
R290 = 2
R291 = 137
R292 = 9
R293 = 1
R294 = 0
R295 = 44
R296 = 5
R297 = 5
R298 = 5
R299 = 1
R300 = 0
R301 = 21
R302 = 23
R303 = 1
R304 = 15
R305 = 4
R306 = 97
R307 = 248
R308 = 67
R309 = 195
R310 = 195
R311 = 195
R312 = 195
R313 = 195
R314 = 255
R315 = 255
R316 = 255
R317 = 255
R318 = 255
R319 = 3
R320 = 0
R321 = 10
R322 = 0
R323 = 0
R324 = 0
R325 = 1
R326 = 6
R327 = 53
R328 = 117
R329 = 11
R330 = 0
R331 = 100
R332 = 0
R333 = 0
R334 = 0
R335 = 1
R336 = 6
R337 = 53
R338 = 117
R339 = 11
R340 = 0
R341 = 0
R342 = 0
R343 = 0
R344 = 0
R345 = 0
R346 = 2
R347 = 0
R348 = 0
R349 = 0
R350 = 0
R351 = 0
R352 = 0
R357 = 40
R367 = 0
R411 = 0

Hello Maksymilian,

Apologies for the delay. I will be testing your configuration to determine the issue and will provide you an update by the end of Monday.

Regards,

Kia Rahbar

Hi,

On this couple days when i observe registers i recognize that i always have LOPL and LOFL, but i never seen LOR (on live read R14 register and R20 interupt register - never clear it yet, just read). I double check 1PPS signal from GPS and from generator and im sure that its ok. Im trying to change phase or lost of signal, but never have LOR. It is posible that my device newer recognize reference signal?

Hello Maksymilian,

Can you please inform me whether the PRIREF_VALSTAT and SECREF_VALSTAT are high or low? These two bits will determine whether your input reference is valid.

Regards,

Kia Rahbar

Hi Kia,

both PRIREF_VALSTAT and SECREF_VALSTAT are low (R411 in reg map attached to my post)

Hello Maksymilian,

Please enable the amplitude detector and set the amplitude detector to CMOS Slew Rate Detector Mode. For a 1PPS input, the amplitude detector must be configured in this fashion.

Regards,

Kia Rahbar

Hi Kia,

still the same. I tried already increase validation timer and modify 1 PPS Phase detector and its still doesnt lock.

My schematic hardware is simple and tested with other PLL from Silicon Labs:

1 PPS signal on PRIREF_P pin :

Status regs from running hardware:
R14 = 240 (LOPL_DPLL, LOFL_DPLL, HIST, HLDOVR is high, the rest - low)
R20 = 240 (same as R14, so i think that LOR never get high)
R13 = 8 (LOL_PLL2 only - i dont use APLL2)
R411 = 0 (PRIREF and SECREF are not valid)

My configuration:

My configuration file from TICS Pro:

R0	0x000010
R1	0x00010B
R2	0x000235
R3	0x000332
R4	0x000404
R5	0x00050E
R6	0x000617
R7	0x00078E
R8	0x000802
R10	0x000AC8
R11	0x000B00
R12	0x000C1B
R13	0x000D08
R14	0x000E00
R15	0x000F00
R16	0x001000
R17	0x00111D
R18	0x0012FF
R19	0x001308
R20	0x001420
R21	0x001501
R22	0x001600
R23	0x001755
R24	0x001855
R25	0x001900
R26	0x001A00
R27	0x001B00
R28	0x001C01
R29	0x001D13
R30	0x001E40
R32	0x002044
R35	0x002300
R36	0x002403
R37	0x002500
R38	0x002600
R39	0x002702
R40	0x00280F
R41	0x002900
R42	0x002A01
R43	0x002BC2
R44	0x002C00
R45	0x002D0C
R46	0x002E11
R47	0x002F07
R48	0x003050
R49	0x00314A
R50	0x00321E
R51	0x003318
R52	0x003418
R53	0x003513
R54	0x003600
R55	0x003700
R56	0x00380F
R57	0x003900
R58	0x003A0F
R59	0x003B00
R60	0x003C0F
R61	0x003D00
R62	0x003E0F
R63	0x003F18
R64	0x0040BE
R65	0x0041BC
R66	0x00421F
R67	0x0043C7
R68	0x004408
R69	0x004500
R70	0x004600
R71	0x004700
R72	0x004833
R73	0x004900
R74	0x004A00
R75	0x004B00
R76	0x004C00
R77	0x004D0F
R78	0x004E00
R79	0x004F01
R80	0x005080
R81	0x00510A
R82	0x005200
R83	0x005307
R84	0x005480
R85	0x005500
R86	0x005600
R87	0x00571E
R88	0x005884
R89	0x005980
R90	0x005A00
R91	0x005B14
R92	0x005C00
R93	0x005D07
R94	0x005E80
R95	0x005F00
R96	0x006000
R97	0x00611E
R98	0x006284
R99	0x006380
R100	0x006429
R101	0x006501
R102	0x006622
R103	0x00670F
R104	0x00681F
R105	0x006905
R106	0x006A00
R107	0x006B64
R108	0x006C00
R109	0x006DC3
R110	0x006E50
R111	0x006F00
R112	0x007000
R113	0x007100
R114	0x007200
R115	0x007303
R116	0x007401
R117	0x007500
R118	0x007600
R119	0x007700
R120	0x007800
R121	0x007900
R122	0x007A00
R123	0x007B28
R124	0x007C00
R125	0x007D11
R126	0x007E79
R127	0x007F7A
R128	0x008000
R129	0x008101
R130	0x008200
R131	0x008301
R132	0x008401
R133	0x008577
R134	0x008600
R135	0x00872B
R136	0x008800
R137	0x008928
R138	0x008AE5
R139	0x008B03
R140	0x008C02
R141	0x008D00
R142	0x008E01
R143	0x008F01
R144	0x009077
R145	0x009101
R146	0x009289
R147	0x009320
R149	0x00950D
R150	0x009600
R151	0x009701
R152	0x00980D
R153	0x009929
R154	0x009A24
R155	0x009B32
R156	0x009C01
R157	0x009D00
R158	0x009E00
R159	0x009F00
R160	0x00A0FC
R161	0x00A132
R162	0x00A200
R164	0x00A400
R165	0x00A500
R167	0x00A701
R178	0x00B200
R180	0x00B400
R181	0x00B500
R182	0x00B600
R183	0x00B700
R184	0x00B800
R185	0x00B9F5
R186	0x00BA01
R187	0x00BB00
R188	0x00BC00
R189	0x00BD00
R190	0x00BE00
R191	0x00BF00
R192	0x00C050
R193	0x00C119
R194	0x00C219
R195	0x00C300
R196	0x00C400
R197	0x00C51D
R198	0x00C600
R199	0x00C700
R200	0x00C81D
R201	0x00C900
R202	0x00CA00
R203	0x00CB00
R204	0x00CC15
R205	0x00CD00
R206	0x00CE00
R207	0x00CF15
R208	0x00D000
R209	0x00D114
R210	0x00D200
R211	0x00D316
R212	0x00D400
R213	0x00D514
R214	0x00D600
R215	0x00D716
R216	0x00D80F
R217	0x00D900
R218	0x00DA00
R219	0x00DB19
R220	0x00DC6E
R221	0x00DD00
R222	0x00DE03
R223	0x00DF0D
R224	0x00E047
R225	0x00E100
R226	0x00E200
R227	0x00E319
R228	0x00E46E
R229	0x00E500
R230	0x00E603
R231	0x00E70D
R232	0x00E847
R233	0x00E910
R234	0x00EA10
R235	0x00EB01
R236	0x00EC86
R237	0x00EDA0
R238	0x00EE00
R239	0x00EF01
R240	0x00F086
R241	0x00F1A0
R242	0x00F200
R243	0x00F33F
R244	0x00F43F
R249	0x00F921
R250	0x00FA00
R251	0x00FB01
R252	0x00FC2D
R253	0x00FD00
R254	0x00FE00
R255	0x00FF00
R256	0x010000
R257	0x010101
R258	0x010200
R259	0x010301
R260	0x010402
R261	0x010580
R262	0x010601
R263	0x01072A
R264	0x010805
R265	0x0109F2
R266	0x010A00
R267	0x010BA0
R268	0x010C04
R269	0x010D00
R270	0x010E02
R271	0x010F96
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x011316
R276	0x011416
R277	0x011516
R278	0x011600
R279	0x011700
R280	0x011800
R281	0x011900
R282	0x011A00
R283	0x011B00
R284	0x011C1E
R285	0x011D1E
R286	0x011E00
R287	0x011F00
R288	0x012000
R289	0x012100
R290	0x012203
R291	0x0123CD
R292	0x012409
R293	0x012501
R294	0x012600
R295	0x01272C
R296	0x012809
R297	0x012909
R298	0x012A09
R299	0x012B01
R300	0x012C00
R301	0x012D1C
R302	0x012E1E
R303	0x012F01
R304	0x01300F
R305	0x013104
R306	0x013261
R307	0x0133F8
R308	0x013443
R309	0x0135C3
R310	0x0136C3
R311	0x0137C3
R312	0x0138C3
R313	0x0139C3
R314	0x013AFF
R315	0x013BFF
R316	0x013CFF
R317	0x013DFF
R318	0x013EFF
R319	0x013F03
R320	0x014000
R321	0x01410A
R322	0x014200
R323	0x014300
R324	0x014400
R325	0x014501
R326	0x014606
R327	0x014735
R328	0x014875
R329	0x01490B
R330	0x014A00
R331	0x014B64
R332	0x014C00
R333	0x014D00
R334	0x014E3D
R335	0x014F09
R336	0x015000
R337	0x015198
R338	0x015296
R339	0x015300
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x015900
R346	0x015A02
R347	0x015B00
R348	0x015C00
R349	0x015D00
R350	0x015E00
R351	0x015F00
R352	0x016000
R357	0x016528
R367	0x016F00
R411	0x019B0C

Hello Maksymilian,

Apologies for the delay. I spoke with my team and we believe we have determined your issue.

The cause for your issue is that your XO input must have a maximum ppm accuracy of 4.9 ppm when using a 1PPS reference and a XO frequency of 12.8 MHz. The maximum allowable ppm error of 4.9 ppm is calculated using the following equation: max XO ppm = 1PPS cntr value (shown below)/ XO frequency (in MHz) = 63/12.8 = 4.9 ppm

If the ppm accuracy of the XO does not meet this requirement you will not be able to lock to the 1PPS input.

Also please note that I was incorrect about enabling the amplitude detector control. Please disable this feature.

Regards,

Kia Rahbar

Hi Kia,

we try to use other generator LINK and we multiple frequency x3 with this LINK (we use rigol dg5252 synchronized to external GPS earlier just for test). Now my configuration looks like:

Still cant lock and no valid reference in R411. We check raw register setting and recognize that R46:

is set to 0x11 (AC-Differential (external termination)) for both reference. I think that it should be CMOS or DC-differential, but i dont see option to change it in TICS Pro. Im not shure that i can change it raw without consecuences in other settings (when i change it in raw registers and try to change some other options in GUI TICS pro overwrite it everytime).

We're figthing with this about 3 weeks and we really need to make this work. Our clients wont wait forever.

[PS]

We're already validate our generator and its much better that 1ppm ( device does not allow for a more accurate measurement). 1PPS phase detector fails all time - when we disable it R411 says that signal is valid but stil doesnt lock. Witch flag says that 1PPS phase detector is ok?

Hi Kia,

i load and program your configuration and its better now. PRIREF is valid (R411), chip switch to PRIREF (R20[3]), but stil cant lock (LOFL and LOPL flags - valid reference is working for 3 hours).

When i load your file TICS Pro show error:

There is a lof of non-exists register in TICS Pro . Can u send a proper device profile?

Hello Maksymilian,

The profile is correct. I created the configuration using the internal version of the GUI, so there are extra register that are not required for your configuration. This is why it skips those registers. 

Please try reloading the file I had sent, then press the soft-reset chip, and then perform a readback of the status registers numerous times for a couple minutes. If you do not see the LOFL and LOPL go low, then perform another soft-reset chip and perform more readbacks of the status register.

From a profile standpoint there should be no more changes required. I have tested the configuration on multiple devices and on the external version of TICS Pro and have not seen any issues.

Regards,

Kia Rahbar

Hi Kia,

thanks for helping, your configuration almost resolve my issue. To make this work i need to manually change reference type to CMOS (R46 to 0x88) DC-coupled (TICS Pro doesnt support this option). When i change it a able to lock in 3-5 minutes. But its a very dangerous issue witch this DPLL. When it start working while there is no valid reference (stable GPS fix) or reference becomes invalid (switch off 1PPS signal when GPS doesnt fix) after lock DPLL never lock again (wait 14h for LOPL flag, LOFL clear pretty fast). I need to perform soft reset to get lock. Its bad because 125 MHz is used for the rest of switch and i need to keep it not disturbed.

Is there any other option to force re-lock without soft-reset?

Is there a flag for valid history? How do i now that chip is in holdover after loose reference and have valid history to hold signal?

Hello Maksymilian,

You're welcome!

A possible reason for why you may not be able to relock is that there is a drift in the accuracy due to the tuning word history when the device is in holdover. Please try turning off the tuning word history as shown below and see if that solves your issue.

Unfortunately, we do not have a flag for valid history.

To determine if the device has entered holdover, the HLDOVR flag can be used. If the flag is high the device is in holdover. The register associated with this flag is R14[4].

Regards,

Kia Rahbar

Hi Kia,

disable Tunning Word History doesnt solve my problem. Still cant relock. I try to get some delay to PPS signal after lock (even 3000 ns phase offset) and DPLL works fine (lost of lock and try to relock). Problem is only if there is lost of signal (even for a very short time). I see that device run in holdover mode, after it recognize a valid reference it clear HLDOVR flag and try to lock. Is there any interactive register to force relock without soft reset? For now device doesnt react for changing in SRAM (i use direct write by I2C) without soft-reset.

Can u change my configuration for 19.440 MHz OCXO? Maybe it will be better (12.8 MHz is out of stock).

3463.Q100_max.tcs

Hello Maksymilian,

Unfortunately, the only way to force relock is with a soft reset.

Yes, a 19.44 MHz OCXO will provide a greater ppm valid range (3.24 ppm (63/19.44)) than the 60 MHz XO input (1.05 ppm (63/60)), so it will be much easier for the device to relock to the 1PPS input.

I would recommend making the changes on your end first since you have it operating correctly on the initial lock. Please follow these steps:

1. Load the working configuration and get the 1PPS to lock.

2. Navigate to the XO page and input the new 19.44 MHz XO frequency as shown below.

3. Navigate to the set outputs page and click calculate frequency plan as shown below.

4. Perform a soft-reset and readback the status bits to see if everything is locking properly. If it is, save the file and load it again to try your relock test again.

I can make the update and test the configuration next week if you are not able to get it working on your end.

Also another test you can perform is to increase the tuning word history count and delay. This will allow for the holdover frequency to be much more accurate when you are in holdover and will allow you to relock much easier.

Regards,

Kia Rahbar

Hi Kia,

we do some test and we see that problem witch relock is only when we loose signal and switchover appears. We even try to make reference "messy" ( DPLL loose LOPL flag)  and we gave the correct signal again. if the switchover event does not occur DPLL can lock pretty fast. In this configuration auto-revertive doesnt work (need soft-reset anyway). Is there a posibility to fix DPLL on PRI_REF and block switchover? We try to set manual holdover on PRI_REF, but even when we choose first reference and disable second there is still switchover event while 1PPS signal get valid/invalid. We really need to make 125 MHz clock not disturbed and we want to hold 1PPS signal from DPLL if GPS loose lock. IF DPLL cant go from holdover to lock without host ingerations (soft-reset) it is not usable in our application (we wait 14h for lock and doesnt have it).

Hello Maksymilian,

Maksymilian Jaroc said:

Is there a posibility to fix DPLL on PRI_REF and block switchover?

By disabling the tuning word history, our goal was to mimic having the DPLL only lock to PRI_REF. Disabling the tuning word would act as if we were on initial startup every time the 1PPS becomes valid.

Can you please provide me the ppm accuracy of the output before DPLL lock, during DPLL lock, and during holdover? Based on the holdover frequency, we can set the tuning word history to make the holdover frequency more accurate so that we can recover from holdover.

Regards,

Kia Rahbar

Hi Kia,

we are running this DPLL now, we can lock in 3-5minuts (your configuration works very good), but sometimes DPLL wont try to synchronize APLL1 and stay in freerun (we can force him to rerun by disable and enable - R252[0]. The same operation we can do when we want to relock after loose reference). We see that DPLL synchronize APLL1 by Fraction N Divider (registers R110 - R114). At start he had 0x5555555555, DPLL change this value when it try to get lock, but sometimes he cant get action. Reference is valid and stable, uC get reset and initialize chip form 0. We can have software fix for that (if we see that he doesnt change it we can force him to). Have you a way to avoid this?

Our start and load sequence is:
Release reset pin and immediately put him in soft-reset state 
Write all registers (R12 is still in soft-reset)
Release soft reset and wait for lock

Thanks!