Other Parts Discussed in Thread: SN74AXC8T245EVM, LMK5C33216, LMK5B33216
Hello,
I try to follow the test in the forum :"LMK05028: How to use GPS PPS as the reference clock to prevent output frequency drift?"
Bellow is my test:
- Configuration load : LMK05028_1PPS_config_40MHz_out_onboard_XO_and_TCXO_V2.tcs, I use the EVM.
- Input PPS : connected IN0_P, 1V8, Duty cycle 50%. The signal is OK in the oscilloscope. IN0_N is connected to 50 ohm cap.
For my test, I use an EVK-M8T GNSS Evaluation Kit (EVK-M8T). I configure the PPS to have a Duty cycle 50% instead of 10%, 3V3. I use an SN74AXC8T245EVM (TI) for having 1V8. The EVK-M8T GNSS is connected to the GNSS ANTENNA.*
I follow this procedure (from Kia Rahbar):
1. Load the above configuration.
2. Press a soft-reset chip.
3. Readback your status registers.
- It will take about 5-10 seconds for the reference to validate (REF0VALSTAT to go high), about 5-10 seconds for the HLDOVR1 flag to go low, about 20-25 seconds for the LOFL_DPLL1 flag to go low, => That is OK
- about 2-3 minutes for the LOPL_DPLL1 flag to go low. => LOPL_DPLL1 flag is always high
Results :
- I have 40.0014 MHz,
- I have frequency drift,
- Always LOPL_DPLL1 high
My questions is what do you use for generating the Input PPS connected to IN0_P to have LOPL_DPLL1 low?
Thank you,
Patrice