LMK5B33216: What is the purpose of the DPLLs preceding the APLLs

Hi Ali,

Not so much the "wider" but instead more "narrow" to allow low frequency inputs such as 1-PPS. The APLL would require "impossible" loop filter components (like 10 F caps) to achieve a narrow LBW such as 0.01 Hz, which the DPLL has no trouble creating because it's all numbers/digital.

Does this help?

Regards,

Jennifer

Thanks Jennifer. Just so I understand better: if I have a  high quality 187.5MHz reference on IN1 and a 48MHz TCXO feeding the XO input and want to cascade APPL3 to APPL2 to get a VCO2 frequency of 5625.0MHz, should I use DPLL3 and have it use IN1 or should I have APPL3 directly use IN1 as its reference.

Thanks

Hi Ali,

1. What is your full frequency plan?
2. What are your jitter requirements? Depending on how stringent, we can either disable DPLL3/APLL3 or enable it.

Regards,

Jennifer

Hi Jennifer,

My full frequency plan is as follows:

Inputs:

• XO: 48MHZ (Driven by TCXO)
• IN0: 187.5MHz (driven by LMX1204 LOIGCLKOUT)
• IN1: 48MHz (unknown quality)
• No automatic failover required

Outputs:

• OUT0: 25MHz/V1P8
• OUT1: 100MHz/LVDS
• OUT2: 100MHz/LVDS
• OUT3: 100MHz/LVDS
• OUT4: 100MHz/HCSL
• OUT5: 100MHz/LVDS
• OUT6: 100MHz/LVDS
• OUT7: 100MHz/LVDS
• OUT8: 375MHz/LVDS
• OUT9: 375MHz/LVDS
• OUT10: 187.5MHz/LVDS
• OUT11: 187.5MHz/LVDS
• OUT12: 187.5MHz/LVDS
• OUT13: 187.5MHz/LVDS
• OUT14: 375MHz/LVDS
• OUT15: 156.25MHz/HCSL

The 375MHz and 187.5MHz outputs should be low phase noise.

My plan was to use IN0 (187.5MHz)  as DPLL3 reference in Manual Holdover and then run APLL3 with the XO (?). I was going to bypass DPLL2 and use APLL3 as the reference for APLL2 @ 5625MHz. Then use the dividers to generate 375/187.5MHz and OUT15 @ 156.25MHz from APLL2. I also planned on using APLL3 as the source for the 25/100MHz outputs.

Hopefully that all makes sense ;)

Thanks

Hi Ali,

Ali Ghorashi said:

My plan was to use IN0 (187.5MHz)  as DPLL3 reference in Manual Holdover and then run APLL3 with the XO (?)

The XO is required for APLLx to generate the outputs. DPLL inputs allow the outputs to lock to the reference, switch between references when one lost, and/or stay in holdover when all references are lost.

Ali Ghorashi said:

I was going to bypass DPLL2 and use APLL3 as the reference for APLL2 @ 5625MHz. Then use the dividers to generate 375/187.5MHz and OUT15 @ 156.25MHz from APLL2. I also planned on using APLL3 as the source for the 25/100MHz outputs.

You can bypass DPLL2 and use DPLL3 input only (such as 187.5 MHz to IN0), then cascade APLL2 to reference APLL3 so that all outputs generated by APLL2 and APLL3 would have the same reference input from DPLL3.

375 MHz and 187.5 MHz can be generated by higher performance VCO2 (APLL2) = 5625 MHz.

Other outputs: 25 MHz, 100 MHz, 156.25 MHz can be generated by BAW VCO3 (APLL3) = 2500 MHz to achieve the best jitter.

-Riley

Thanks Riley,

The datasheet mentions that the loop bandwidth on the DPLLs can be set between 1mHz to 4KHz but on TICSPro, I don't see where that value can be directly programmed. I looked through the registers in the user's guide and came up empty handed.

How do you program the loop bandwidth? Is there a formula I should use? I tried using "Step 6" in TICS Pro but after the script gets done running, I get bogus VCO3 values (see attached).

I have attached my TICS pro file for your reference. I'm using TICS Pro v1.7.6.2.

LMK5B_tics_pro_48GSPS_Operation_v6.tcs    2068.Setting_DPLL_BW.pdf

Thanks Riley. I'll try that. Is there a formula for the DPLL bandwidth?

We don't have a specific formula. DPLL LBW is also an input to calculate other DPLL register settings that TICS Pro handles internally when running scripts. You can input DPLL LBW and run the software to handle this calculation.

-Riley

Hi Riley, I tried your recommendation by disabling REF0/REF1 individually and running the script. I got same results as before (DPLL3 set to 3750 MHz) regardless of which REFx I disabled. 

Hi Ali,

I will run your config and check the FB path values. Will update during next weel.

-Riley

Riley Nguyen said:

I will run your config and check the FB path values. Will update during next weel.

Hi Riley,

Were you able to recreate the problem on your end?

Thanks Riley.

I tried to follow your suggestion but got confused. Are you saying that TICSPro is working as expected and the values I have are incorrect? In that case, I don't understand what I was doing wrong. I tried setting the DLL3 to the values you showed in your picture and re-ran the script and got a different result. The DLL3 R Div values changed to 2 and 2. Is that the expected behavior?

What I entered:

What I got after pressing "Run Script"

How can I figure out what the starting values for DLL3 R Div and Div#1 & #2 should be? It seems to me that the numbers I was using would result in the same APPL3 and DPLL3 VCO frequencies prior to pressing the  "Run Script" button but clearly there are right and wrong starting points.

What I had before which resulted in bad APPL3 VCO frequencies:

Hi Ali,

As narrowing down to Manual holdover with REF1 causing miscalculation in DPLL settings, if you need to run script, you can set to auto mode with single REFx available so the calculation can properly update.

Or you can use the above DPLL settings I shared to manually update DPLL3 Div box. This way, VCO3 is updated to 2500MHz and you don't have to run script again.