PLL1 and PLL2

Hello Everyone, I am trying to design a clock file (LMK04828 or LMK04828B in TICS pro double loop) for RFSOC 4x2 for VCO1/Clock distribution frequency 3000Mhz  (In range as per TICS manual 2920 - 3080 MHz). I am using TICS pro software to design .tcs files and export hex register files in .txt form to FPGA and PLL1 is not locked. I am attaching a .tcs file here. Primarily, with the default clock file, both PLLs are locked along with ADC and DAC, and all four LEDs turn on.
In contrast, when in try to design a clock file with CLK IN 1 100MHZ LVDS and no Ext. Ref. Cbishnu_LMK04828B_rfsoc4x2default_try.tcslk with 160 MHZ VCX0 as in RFSoC clocking Scheme.