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I am designing clock file LMK04828B for RFSOC4x2 board, with SLKin 100 Mhz, External VCO 160, and VCO/Clock Dist. Frequency 3000 Mhz. PLL1 and PLL2 are not locking.
cliff_try (2).tcsI am attaching a .tcs file as well in the attachment. Please help.
Hello,
Have you changed the Loop filter components on your EVM? If you are using the EVM, and replaced the Crytek 122.99 MHz VCXO with your own 160 MHz VCXO then you will need to update the Loop Filter components (capacitors & resistors) on the board in order to achieve lock. You can use our PLLatinumSim tool in order to calculate the correct values to use. Here is a helpful e2e which shows how to configure PLLatinum Sim in order to adjust your PLL loop filter components.
Another note, you should always maximize your phase detector frequency for both PLLs. This will definitely improve performance. I have attached a ticspro config file with higher phase detector frequencies.
Regards,
Will
Hi,
This didn't solve my issues. Pll1 is still not locked. I redesigned a clock. Please have a look. I tried PLLitinum as well.
Bishnu,
Your config looks like it should lock. I am guessing your problem lies in your loop filter. A few questions:
Regards,
Will
Bishnu,
In your other thread you mentioned that you are able to achieve lock with a different configuration? Can you share the .tcs file for that configuration and tell me about that setup?
Regards,
Will
Hello William ,
There are my filesa and configuration.
RFSOC 4x2 board has LEDs to determine whether it is locked or not. In my case, PLL2 is locked. PLL1 led is not on.
I used PLLatinum Sim and found PLL1 is vcx0 = 160, c1 = 100 ng, c2 = 680 nf, and R2 = 39 K ohm KVco is 0.0025 Mhz/V, PLL2 VCO1 = 3000 MHz, c1 = 0.047 nf, c2 = 3.9nf, Kvco = 20 MHz/v, R2 = 0.62 K ohm.
The file where i have PLL2 locked (LED turned on) and PLL1 not locked (LED didn't glow) is the same file as mentioned above.
Thank you.
8244.bishnu_LMK04828B_rfsoc4x2default_try.tcsbishnu_LMK04828B_rfsoc4x2default_try1.tcs