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LMC555: Latch up

Ning Li
Intellectual 770 points

Part Number: LMC555
Other Parts Discussed in Thread: TLC555

Dears,

At present, the circuit we design first outputs a high level signal (2.6V or 3.3V, with a maximum drive current of 20mA) to the second pin of the LMC555CMX chip, and then power on the chip after an interval of tens of milliseconds or even tens of seconds. May I ask whether this use will cause the internal CMOS tube of the chip to produce a latch up effect, resulting in abnormal situations? Or even damage the chip?

Thanks

  • 0
    TI__Mastermind 29035 points

    Hello,

    The absolute maximum voltage and current levels cannot be exceeded that are listed below. If the input of the second chip is getting driven when the chip is off permanent damage may occur. 

    Best Regards, 

    Chris Featherstone

  • 0 in reply to Chris Featherstone
    Intellectual 770 points

    Dear Chris,

    Noted,Customer want to know below question,pls kindly help to check it.

    1) The maximum drive current of the GPIO of the CPU is only 20mA, which may cause permanent damage? So what's the mechanism? Is it the latch effect?

    2) If it is not damaged, just at the beginning of the pin to the high level, and then restore the normal power supply, will lead to the logic error of the LMC555 chip?

    3) If it may be permanently damaged, does it mean that the logic gate chip must also consider the power-on timing?

    Thanks

  • 0 in reply to Ning Li
    TI__Mastermind 29035 points

    Hey Ning, 

    The input current limit to nearly all of our devices is recommended to be 10 mA or less and this is a limitation of the amount of current that ESD diodes can safely handle. We have a very long history with the timer devices and I am not aware of latch up issues regarding the timers. The LMC555 is 24 years old and the data we have is limited to the product datasheet. 

    Ning Li said:
    If it is not damaged, just at the beginning of the pin to the high level, and then restore the normal power supply, will lead to the logic error of the LMC555 chip?

    This scenario would need to be tested in the customers circuit for verification. We don't have latch up test data for this device. There is no data to support an answer for this question. 

    Ning Li said:
    If it may be permanently damaged, does it mean that the logic gate chip must also consider the power-on timing?

    The timer must be at at least the minimum power supply for the internal comparators to be biased properly in order for the logic levels to be valid. If outside input levels to the timer exceed the power supply by more than 300 mV, permanent damage may occur. So power on levels and input levels should be considered when the device is powering on. 

    Best Regards, 

    Chris Featherstone

  • 0 in reply to Chris Featherstone
    Intellectual 770 points

    Hi Chris,

    Thanks for your support,coudle you pls kindly help to check the schematic.

    ThanksLMC555 CIRCUIT.doc

  • 0 in reply to Ning Li
    TI__Mastermind 29035 points

    Hey Ning, 

    I will look over the schematic and will respond within 2 business days. 

    Best Regards, 
    Chris Featherstone

  • 0 in reply to Ning Li
    TI__Mastermind 29035 points

    Hey Ning, 

    We don't have a spice model for the LMC555 so I used the TLC555 to check the general functionality of the circuit. Below you can see that the design shown in the schematic provides a 2.66 ms pulse on the output when the trigger pin is pulled low. I have included my Tina simulation at the bottom of this post. 

    TLC555 Mono.TSC

    Best Regards, 

    Chris Featherstone