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LMX2594: SYNC MODE

KYUNGCHAN NOH
Prodigy 30 points
Part Number: LMX2594

Hi there!!

I am using LMX2594 and want to use a sync mode. 

I have set the PLL as the pic below

There is a problem I want to fix.

When I set fractional mode which is the output of PLL is not a multiple of Fosc, 

(For example Fosc : 100 MHz, Output : 4050Mhz)

The output of PLL looks like there is a fractional spur like below

And It doesn't happen If I use integer mode which is the output of PLL is a mutilication of Fosc.

(For example Fosc : 100 MHz, Output : 4000Mhz)

It looks very clean like below.

This issue specifically occurs only when in sync mode. (when VCO_Phase_Sync = 1)

Anyone know about this problem or how to fix? 

Thanks

  • 0
    TI__Mastermind 21201 points

    Hello Kyungchan, 
    It appears you have an integer boundary spur in the first configuration due to the VCO frequency. 

    Typically, you will need to shift your phase detector frequency a bit to mitigate this issue. 

    Please note you can estimate spurs, phase noise, etc. using PLLatinumSim  

    Do you have a frequency plan? If so, can you provide it so I may better assist you? 

    Regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    TI__Mastermind 21201 points

    Hi Kyungchan,
    I see Noel has responded in a previous thread - I just want to confirm I understand your question correctly to provide the appropriate feedback.
    Are you asking how to mitigate the spurs or are you asking about sync mode? 

    Regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    TI__Guru* 93670 points

    Hi Kyungchan,

    First of all, you are not using the up-to-date TICS Pro because the IncludedDivider value should be 4 not 6. Please use the latest version.

    4150MHz is in fact an integer channel, that is, PLL_NUM =0. Unfortunately, when you enable phase sync, the IncludedDivider makes it a fractional channel. As a result, you have fractional spurs and I believe you want to use a bigger PLL_DEN to randomize the spurs. Yes, bigger PLL_DUN does randomize the spurs and as a result, phase noise gets worst. 

    I checked this in the lab, I think the best configuration is use a smaller charge pump current and a smaller PLL_DEN. 

    with below configuration, charge pump current is 3mA, fpd = 50MHz,

    I can get -70dBc spurs.

    Phase noise is not bad.

    with 3mA charge pump current, you may need to redesign the loop filter. Here is an example.

  • 0 in reply to vicente flores prado
    Prodigy 30 points

    Thank you for the comment!!

    I am asking how to mitigate the spurs in sync mode.

    Because it didn't happen when I don't use a sync mode.

  • 0 in reply to Noel Fung
    Prodigy 30 points

    Thank you for the comment!!

    I think I can fix the problem as you suggested.

    I will try to do it.

    Thank you so much!!