LMK04832-SP: Performance Degradation While Unpowered for Fin0

Robert, let me step in here because I recognize some of this question from https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1320249/lmk04832-sp-powered-off-max-input-voltage.

First, to clarify: when we say 10hrs lifetime, this is cumulative. The testing we performed to arrive at this number used a constant DC current of about 7mA injected into the device at accelerated lifetime temperatures well over 125°C for about 1000hrs (edit: my coworker corrects me, it was 125°C for 1000hrs instead of over 125°C for 100hrs), so the cumulative duration limit of 5mA, 10hrs, 125°C is intended to offer a very conservative limit to account for the limited sample size of our testing (considering the cost, we don't have that many space-grade devices to test). As mentioned before, the duration can also be nominally increased at lower temperatures, since the limit for electromigration acceptability in the affected metal layer derates by about half for every ~20°C increase in temperature. This limit would also apply to AC-coupled inputs, but because the unpowered input behaves as a half-bridge rectifier with a highly-dynamic load consisting of everything on the VDD pins (including other unpowered LMK04832-SP inputs and the LDO or other device providing the 3.3V rail), it's impossible for us to give strong guidance for the AC-coupled case. The whole reason we inserted this limit into the datasheet was for the DC-coupled SYNC/CLKin0 acting as SYNC use case, which presumed a non-continuous pulse; so I wouldn't assume that DC-coupled and AC-coupled behaviors are comparable.

Second, upon going back through my post and reviewing the original documentation on how we arrived at our numbers in the datasheet, it occurs to me I actually misremembered the mechanism of concern - it's not ESD routing, it's actually a substrate current path through an input buffer structure. The ESD elements are sufficiently sized that there isn't much concern with electromigration on those elements, but one of the PMOS input buffer elements nominally has a substrate bias at VDD, so if the device is unpowered, a path exists from the drain of the PMOS to the floating substrate node. This doesn't change my conclusion, I just wanted to clarify the correct affected element.

To your questions: we did not test Fin0 directly for cumulative lifetime stresses. I gave a previous answer to you about this, but I may not have been clear, so let me clarify the reasoning:

• Fin0 and Fin1 (CLKin1) are similarly structured, aside from some biasing elements which are nominally high-impedance, and the LOS circuitry for MOS mode which is not a concern.
• CLKin1 and CLKin0 are also similarly structured. So plausibly Fin0 and CLKin0 should be similarly structured in bipolar mode.
• The primary current path is a structure in the input buffer which sees high current through the metal layer just above the drain-to-substrate connection - the substrate is connected to VDD. For current to pass through this path, it must first overcome a nominal diode drop.

The reasoning above might be invalid if the sizing of the metal paths in the Fin0 input structure are different from Fin1/CLKin1 or CLKin0, and the input voltage is high enough to result in a potentially-damaging (mA-range) input current into Fin0; or if the temperature is high enough that the forward voltage of the diode is significantly reduced (this is extremely difficult to predict without models, but it's comfortably above the 125°C limit suggested). So I feel confident telling you that the 10hrs lifetime limit is not an applicable concern in this case, since the input amplitude at Fin0 as described in your previous E2E post isn't large enough to get mA-scale currents at any kind of input structure that could conceivably result in a substrate path for current, regardless of what the structure ultimately is.

Above ±300mV into unpowered Fin0, I don't know if Fin0 will be affected by electromigration concerns - my concern would grow exponentially in proportion to the input amplitude (and the consequent current into the substrate paths), and perhaps polynomially with temperature (for whatever that's worth).

I apologize if these answers are a little unsatisfying. LMK04832-SP didn't take cold-sparing or unpowered input usage into account during the design cycle, so we ended up discovering after the fact that there is some room for these conditions, but it becomes complex to circumscribe anything other than a very conservative limit and some vague restrictions aligned with absolute maximum ratings. Future designs will definitely take cold-sparing or fail-safe input design into account.