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LMK03806: PLL not locking

David Wende
Intellectual 680 points
Part Number: LMK03806

Hello

I am using the LMK03806BISQE_NOPB part on my board.

The uWire is working; it was tested by toggling the FTEST/LD as per the suggestion in the datasheet.

I am loading registers as per the attached figure. The relevant schematic is also shown below.

For the time being I am interested only in CLK2. The other outputs can remain disabled.

There is no output at CLK2, and in addition the LD on pin 33 is remaining low.

Any ideas on finding the fault here?

Thanks for any help.

David

lmk_sch.pdf

  • 0
    TI__Expert 6055 points

    Hello,

    We will take a look at this on the bench and get back to you by EOD Thursday 4/11.

    Best,

    Cris

  • 0 in reply to Cris Kobierowski
    Intellectual 680 points

    Just some more info.

    I changed the contents of R10 to 0x1655_400A in order to output the divided OSCin to OSCout0 and check that the input stage is working ok.

    Yes - I am seeing 20MHz at OSCout0.

    The LD output is still at 0, so my guess is that for some reason the PLL is not locking.

    However, even if this is correct, shouldn't I get SOME SORT of clock output at CLK2 (even if VCO is not the correct frequency)?

    David

  • 0 in reply to David Wende
    Intellectual 680 points

    And some more info.

    I changed the programming to the below, and this caused the following changes:

    1. LD pin is now high.

    2. 100MHZ output on CLK8 and CLK9

    3. Still no clock outputs on the other clocks.

    Note that I am not programming R4, and the default power-up divider for CLK8_9 should be 25, however I am measuring 100MHZ for these clocks.

    New programming is:

    Register Data/Address Action


    R0 0x0002_0000      Reset=1
    R0 0x0000_0060      1_0_DIV=3
    R1 0x0000_0021      2_3_DIV=1
    R3 0x0000_0023      6_7_DIV=1
    R6 0x1111_0006       Clk 3,2,1,0=LVDS
    R7 0x1111_0007       Clk 7,6,5,4=LVDS
    R8 0x1111_0008       Clk 11,10,9,8=LVDS
    R9 0x5555_5549      Magic
    R10 0x1655_400A    OSCout0 enabled, div 5
    R11 0x37F0_000B    No Sync, No Ext XTAL
    R12 0x130C_006C   LD_MUX (DLD)
    R13 0x3B02_800D   Readback, GPIO 0
    R14 0x0200_000E    GPIO 1
    R16 0xC155_0410    Magic
    R26 0x8F40_0F1A    PLL_Delay_Cnt, PLL_CP
    R28 0x0010_001C    PLL_R=1
    R29 0x0180_00BD    OSCin_Freq=100, PLL_NCAL=5
    R30 0x0500_00BE     PLL_N=5, PLL_P=5

  • 0 in reply to David Wende
    Intellectual 680 points

    I think the issue is solved.

    I started using the TICS PRO software instead of PLLatinum.

    Configured inside the TICS, loaded the register export into the device, and now all output are working.

    David