LMX2492: Deasserting SWRST early causes failure 1% of the time

We have noticed that if the SWRST bit is deasserted before programming the other registers the PLL does not lock ~1% of the time, but if it is only deasserted after the higher registers it seems fine.

So this sequence works 99% of the time and fails ~1% of the time

1. R2 = 0x5
2. R2 = 0x2
3. R39, R38...
4. R2 = 0x2
5. R0 = POR value 

This sequence seems reliable.

1. R2 = 0x5
2. R2 = 0x2
3. R39, R38...
4. R2 = 0x2
5. R0 = POR value 

I think this is related to these threads

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1055280/lmx2492-wait-time-after-chip-reset

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/971568/lmx2492-soft-reset-of-lmx2492-fails-occasionally

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1183461/lmx2492-lmx2492-hangs-after-multiple-reprogramming/4479612

It would be nice to get a recommended sequence in the data sheet as requested by this thread, especially since it seems that if we look for the reset sequence in other parts we will get the wrong sequence (LMX2595)

e2e.ti.com/.../lmx2491-unclear-guideline-in-datasheet-regarding-programming-order