LMX2572LP: LMX2572LP multi chip sync fail

Hi Hailiang,

Did you make INPIN_IGNORE=0? 

This is a Cat.3 sync, the timing of SYNC signal is critical. From your timing plot, I cannot tell if the timing requirement is met. Could you make a better measurement so that we can measure the timing clearly?

Hi Noel Fung,

Thanks for your reply.

我们已经设置INPIN_IGNORE=0，

下图是更细节的图，时序是否能够看得清？

Hi Hailiang,

We need something like below. Purple trace is the SYNC pulse; pink trace is the OSCin clock. 

Please also try to move the OSCin clock 2ns to the left.

考虑到FPGA将SYNC信号延时的方便性，我们将ync上升沿向右延时2.5ns，同步依然失败。  

另外，我们还将SYNC信号向右延时5ns，依然同步失败，波形如下：

Hi Hailiang,

I have no problem making two EVM synchronized in the lab, using your configuration.

Your measured waveforms are not "square", hopefully this is just a scope and measurement issue.

Assuming these signal are good, I need to check your hardware, could you share your schematic?

BTW, here is the .tcs file I used for the experiment.

e2e2572lp.tcs

Hi Noel Fung:

我们也有使用两块LMX2572LP的EVM同步成功，寄存器配置也都一样，用EVM寄存器放到我们的板卡上运行同步失败。

测量波形看起来不够方可能是示波器测试引起的，暂时假设实际信号完整性没问题。

附件是PLL部分的原理图。

另外，我使用中文回复是否会影响到你的理解？如果有影响我可以尝试自己先翻译成英文再发出来。

谢谢。

SCH-LMX2572LP.pdf

Hi Hailiang,

The LVDS output clock from LMK00304 (U56) should be DC-couple to a 100Ω differential load.

You only used one output channel from U56 to U62, where are the reference clocks to other LMX2572 came from?

Hi Noel Fung:

LVDS端接方式我把硬件改一下再测试看一下。

我们是做的多卡同步，两张卡是在背板发过来的同步的PXIe_CLK100_P/N时钟作为参考时钟的。

按照你的建议在AC耦合电容之前端接100R电阻，结果还是SYNC fail。请继续帮忙分析一下调试方向，谢谢。