LMK1D2106: Bank-to-Bank Output Skew

Tool/software:

Hello, 

I am designing around the LMK1D2106 part for a high-speed ADC application where we are fanning out an FPGA LVDS sample clock to > 12x ADCs (can't specify actual count). We've chosen to use this chip cascaded in order to fan out the same signal to all our ADCs with minimal timing skew and near-identical prop delay.

We're planning to use multiple outputs on one bank of the upstream LMK1D2106 part to drive both of the dual inputs on the downstream parts to maximize fanout per part / minimize part count in our design. 

We've got some tight timing requirements for ADC synchronization, and while the output skew within the same bank (tsk,o) and the part-to-part skew (tsk,pp) are defined, there doesn't seem to be a datasheet spec for bank-to-bank skew within the same part. Worst-case we'd assume this is no worse than part-part skew but we'd like to have a more specific number. Understood that the overall timing skew will be a stackup that also includes skew from the first stage tsk,o and the tsk,pp between the 2nd stage ICs.

Could you confirm what the bank-to-bank output skew is for the LMK1D2106 for the case where both inputs are driven by the "same" (i.e. in-phase) signal?

pic of intended configuration below.

(sidenote -- LMK1D2104 could be used for the first stage but same ICs is more BOM-efficient and gives flexibility for an increased fanout ratio in the future)