LMK04828BEVM: Using the SYNC input causes all active clock outputs synchronization

Hi Fan, 
The AE is OoO - 
Give us until end of week - sorry about delay. 

Best regards, 

Vicente 

Hi Fan,

I suspect that you may be using nested zero-delay dual-loop mode, when you should be using cascaded zero-delay dual-loop mode. You can select dual loop 0-delay cascaded mode in the Set Modes menu in TICS Pro. However, I put together a config that may be what you need. I would prefer if you could send over your configuration, so that I can be 100% positive it is what you need, but this should be enough to make sure you have a deterministic relationship between the reference and output phase.

Thanks,

Michael

dual_loop_0_delay_cascaded.tcs

Hello Michael,

Thank you for your reply. The current configuration is configured LMK04828 to Nested Zero-Delay Dual-Loop Mode. All outputs are configured as Device Clock Output (CLKIN0  = 100MHZ; VCXO = 125MHz; CLKOUT = 100MHz) ; I want to use the SYNC input（SYNC pin, without using the sysref function） to trigger the synchronization of all output clocks.

R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010019
R257	0x010155
R258	0x010255
R259	0x010300
R260	0x010400
R261	0x010500
R262	0x010670
R263	0x010711
R264	0x010819
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C00
R269	0x010D00
R270	0x010E70
R271	0x010F11
R272	0x011019
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011400
R277	0x011500
R278	0x011670
R279	0x011711
R280	0x011819
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C00
R285	0x011D00
R286	0x011E70
R287	0x011F11
R288	0x012019
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012400
R293	0x012500
R294	0x012670
R295	0x012711
R296	0x012819
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C00
R301	0x012D00
R302	0x012E70
R303	0x012F11
R304	0x013019
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013400
R309	0x013500
R310	0x013670
R311	0x013711
R312	0x013800
R313	0x013900
R314	0x013A00
R315	0x013BFA
R316	0x013C00
R317	0x013D00
R318	0x013E00
R319	0x013F0B
R320	0x014009
R321	0x014100
R322	0x014200
R323	0x014351
R324	0x014400
R325	0x01457F
R326	0x014608
R327	0x01470E
R328	0x014833
R329	0x014945
R330	0x014A05
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x01540A
R341	0x015500
R342	0x01560A
R343	0x015700
R344	0x01580A
R345	0x015900
R346	0x015A0A
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016105
R354	0x016245
R355	0x016300
R356	0x016400
R357	0x016519
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016819
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E1B
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

BR//Fan

Hi Fan,

I will get back to you soon.

Thanks,

Michael

Hi Fan,

I have reconstructed your setup and tested it in lab. I have had no issues with synchronization, and I think that yours are the result of not synchronizing your dividers. What do you mean when you say you are controlling the SYNC signal? You can synchronize your dividers by pressing the "SYNC Dividers" button in the SYNC/SYSREF tab. Please let me know if you have anymore questions.

Thanks,

Michael

Hello Michael,

Can you show your oscilloscope test waveform?

In my tests, I wanted to use the sync pin inversion to control the synchronization process, and the manual supports connecting external signals via sync pin, or SPI. This test way is my final application.

There are three problems in my lab bench:

1. The waveform between the output channels cannot be aligned, and there is a little deviation;

2. The input(CLKin0) and the output(DCLKoutX) cannot be aligned, that is to say, it is not 0-delay;

3. After power cycle, these waveforms will be phased shifted.This results in inconsistent results every time.

The blue is the input（CLKin0）, and the red and green ones are the two channels（DCLKoutX） of the outputs：

BR//Fan

Hi Fan,

Sorry for the delay. I had to perform a rework to board in order to allow for the VCXO to be input as 125 MHz. I will get to you tomorrow.

Thanks,

Michael

Hi Fan,

The scope shot that I took can be seen below. The yellow sinusoidal signal is the CLKIN0 input signal and the other two are DCLKoutx outputs (blue is 10, orange is 0, respectively). There will be some skew and delays that are the result of wiring and traces that cannot be removed. 0-delay is actually a bit of a misnomer; 0-delay mode actually means that the delay between the input and feedback output (and any outputs synced to that feedback output, which can be selected in the SYNC/SYSREF page by clicking the appropriate SYNC_DISx boxes) will be deterministic. You need to ensure that you are syncing your dividers upon each power cycle to make sure your outputs are phase-aligned. 

I have attached my config file (which is for a LMK04826, which is very similar to the LMK04828 but needs to be translated to a config for a 4828) for more clarification. Furthermore, I would like to see your schematic/setup. Are you using an EVM board? If so, have you reworked the board so that your external VCXO is 125 MHz?

sub_vcxo.tcs

Thanks,

Michael

Hello Michael,

There are a few more points that I need to confirm from your:
1, Is the input signal generated with a signal generator?  or by XO?

2, the waveform is seems not quite right, the oscilloscope's C3 does not show, the M1(orange ) in the graph should be the result of the math function, right?

3, the amplitude of the two DCLKoutx in the waveform is not consistent, the relative difference is nearly 1.5ns. The difference in the output result between the two channels is too big.

4, the EVM can be through the TICS pro to control the sync function, but for the formal application, how do we control it, according to the TICS pro export file can be executed or need to add the sync step in the end?

5,For the power cycle, we fixed the SPI control program into the FPGA to control the LMK04828, and then the whole system together to carry out the power cycle operation. The phase change between the two output channels occurs at the fifteenth.You can help with the experiments on your end, too.

We haven't applied for our EVM yet, some of our current experiments are referencing the EVM to make our own boards, I'll send it to you privately and you help to review the schematic, thanks a lot!

BR//Fan

Hi Fan,

1. The input signal is generated by an SMA100 signal generator.

2. M1 is a math signal - it is C3 - C4, where C3 is the non-inverted output from DCLKout0 and C4 is the inverted output from DCLKout0. 

3. The difference in amplitude is due to the way I fed the signals into the oscilloscope. C2 was measured by taking the two outputs from DCLKout10 and sending them through a balun, whereas M1 was measured by inputting each differential signal to the oscilloscope and relying on the math function to resolve the signal. I will see if I can find an additional balun, so that the amplitudes will be the same, and I can send an additional scope shot. The skew is also a bit larger than it should be, I can resolve that too.

4. The SYNC function can be controlled through various methods (see section 9.7.3.10 in the LMK04828 datasheet), but the easiest method would be to set SYNC_MODE to 1 and input a rising edge to the SYNC pin. That rising edge serves as the "SYNC event" which will synchronize all of the selected output dividers (selected by the SYNC_DISx bit, where x corresponds to the CLKoutx channel, which will be synchronized upon the SYNC event so long as SYNC_DISx is set to 1).

5. I am a bit confused by what you mean here. The phase change between the two output channels occurs at the fifteenth occurrence of what? Have you tried synching the dividers when that happens?

Also, you are more than welcome to send any questions or schematics to my email, m-srinivasan@ti.com :)

Thanks,

Michael