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LMK04828BEVM: PLL1 lock fails when generating DAC Ref Clk from SFP recovered clk in clk104 RF add on card

Vaishnavi Adurti
Prodigy 20 points
Part Number: LMK04828BEVM
Other Parts Discussed in Thread: LMK04828

Tool/software:

Hi,

In our ZCU208 design, we need to generate DAC data using the SFP recovered clock from the PCS/PMA Ethernet. We're attempting to generate the DAC reference clock by programming the CLK104 RF Clock Add-on Card through TICSPRO. We're operating in dual loop mode and providing our SFP Rx recovered clock (62.5 MHz) as clkin2 input for the LMK04828B (U2). We are getting the DAC ref clk out signal but PLL1 in the LMK04828B is not locking. We've confirmed this by programming register R366 (0X016E1B address) to check the PLL1 lock status using the DS1 LED, which is blinking.

Interestingly, when we test with an oscillator input instead of the recovered clock, PLL1 locks successfully.

I am attaching the relevant TICSPRO configuration and clk104 block diagram as specified in UG1437.

Could you advise on how to ensure PLL1 locks when using SFP recovered clock as the input ? Also, could you clarify whether the SFP recovered clock input should be in CLKIN2 or CLKIN0? The documentation isn't very clear on this point.

Thank you

  • 0
    TI__Mastermind 23461 points

    Hello Vaishnavi, 
    I am unsure of how the recovered clock is connected to the LMK04828.
    In one table 6 from AMD/Xilinx it says that the recovered clock is connected to CLKIN0. 
    In the block diagram it shows the recovered clock connected to CLKIN2.

    Where exactly is this recovered clock routed too physically on the board? 

    What are the specs of the recovered clock? 

    You mentioned when you use the oscillator as reference to PLL1 it is able to lock. From the block diagram it the oscillator connected to CLKIN1? 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 20 points

    Hi Vicente,

    I am also unsure if the recovered clock is mapped to clkin0 or clkin2 as its conflicting in different documentation and there are not much designs available using sfp recovered clock for reference.

    Our recovered clk is of 62.5 MHz and is generated from rxoutclk of ethernet pcs pma ip.

    We are mapping our recovered clk to M20,L21 i.e. clk104_sfp_rec_clk_p and clk104_sfp_rec_clk_n as per schematics. 

    Yes the 10Mhz oscillator is connected to clkin1 and with it PLL1 locks. Also if we provide an internally generated clock in FPGA design from oscillator on ZCU208 and mapping it to clk104_sfp_rec_clk_p PLL1 still locks. But only when we provide recovered clock it fails.

    Please share if you have any design or TICSPRO configuration involving sfp recovered clock and its specifications

    Best Regards,

    Vaishnavi

  • 0 in reply to Vaishnavi Adurti
    TI__Mastermind 23461 points

    Hello Vaishnavi, 
    I would need to know how it's configured on the layout. 

    If you choose either of the two CLK inputs for the LMK04828 using the recovered clock - can any of the two inputs result in a lock? 
    Does the recovered clk meet the clkin specs? 

    PLL1 requires a good slew rate to get it to lock. 
    I assume this recovered clock is a square wave, correct? 
    What is the swing and VCM? 

    Best Regards, 

    Vicente