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Tool/software:
Hi,
I have a differential 225MHz clkout to FPGA. LVDS Input side AC-coupling requirement in FPGA is highlighted.
What is the power out dBm need to choose for clkout to meet the FPGA input voltage requirement?
Thanks
Hi Noel,
No - I mean the CLKOUT only not the AUXOUT. Input clk is 1800MHz for CB. We can divide by 8 and take it out as 225MHz for the FPGA.
FPGA accepts AC-coupling for LVDS. Hence we plan to connect the CLKOUT to FPGA.
What would be PWR setting in that case?
Also, can you recommend the proper termination for CLKOUT while connecting to FPGA?
Hi Nandini,
If you use CLKOUT, you have to AC-couple it to the FPGA.
PWR =2 voltage swing is 420mV.