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CDCE6214-Q1EVM: Output divider

Jeff YANG
Mastermind 7950 points
Part Number: CDCE6214-Q1EVM
Other Parts Discussed in Thread: CDCE6214, CDCE6214-Q1

Tool/software:

Hi,

  1. If using the CDCE6214 with an output of 1.8V, could you please confirm whether it is possible to directly adjust the voltage drop to 1.2V using a resistive voltage divider?

  2. Additionally, if a voltage divider is used, will it affect the RMS jitter?

  3. It has been observed that when powering on and importing the previous settings from the txt file, the frequency is not accurate, and it requires a calibrated VCO operation. If we want to ensure that the frequency is as accurate as possible each time, what aspects should we pay attention to?

Thanks!

Jeff

  • 0
    TI__Mastermind 22810 points

    Jeff,

    1. The supply voltage does not support 1.2V. This must be done with external termination (AC-couple the LVCMOS clock, then add a 50-Ohm pull-up to 1.2V and a 50-Ohm pull-down to GND).
    2. I cannot speak to the potential jitter impact of connecting the clock in this way - my recommendation is to ensure that you have proper 50-Ohm impedance matching for all traces connected to the clock signal.
    3. After writing PLL settings to the CDCE6214, you MUST recalibrate the PLL to achieve lock with the proper frequency.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    1. Is this connection method correct? AC-couple close to Device end.

    2. We set OUT2P at 1.8V by default; after passing through a 50 & 50ohm voltage divider, only a DC level of 0.9V remains; however, we hope for an output at around 1.2V. Can we adjust this by changing one of these two resistors?

    3. After writing PLL settings: does this refer to which register positions? Or can we set R0~R85 all at once before performing recalibration?

  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    I would change both resistors to ensure that you still have an impedance of 50-Ohms for minimal reflections. You can try this using 75-Ohms in place of R48 and 150-Ohms in place of R51 (referring to OUT2_P).

    For register programming, you can write all of the settings and then recalibrate the PLL.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    1. In general LVCMOS architecture, AC coupling configuration is less commonly used. It is typically more common in LVDS or other formats.
    2. Our backend IC is a UFS IC. Currently, our EVB has no experience with AC coupling. Could you please share your experience with using AC coupling in LVCMOS?
  • 0 in reply to Li YuanKan
    Prodigy 200 points

    Based on the calculation formula 1.8V / (75 + 150) = 8mA, but the LVCMOS output capability is only 6mA. Does this indicate a driver insufficiency issue?

    Is it necessary to adjust the impedance matching?

  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    My apologies for the delay - I will provide a response on Monday.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    TI__Mastermind 22810 points

    Li,

    What is the minimum/maximum voltage (as well as the voltage when no clock is actively being applied) that your receiver can tolerate?

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    maximum:1.26V  minimum:0.819 typical:1.2V

  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    What you should be able to try is, without needing any AC coupling capacitors or pull-ups, adding a 100-Ohm resistor to GND near the receiver. This can be tested on the EVM by substituting R39 and R43 in the below image (OUT1) with 100-Ohm resistors. This should allow for meeting the proper 1.2V swing with minimal reflections at the receiver.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    We are using the "single-end LVCMOS-P" configuration. Does it have an internal voltage divider design? (OUT1P = 1.8V) Therefore, after connecting "R39 = 100Ω," will the voltage become "1.2V" due to internal voltage division?

  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    The driver outputs 1.8V LVCMOS with a 50-Ohm driver. The voltage at the receiver is divided down by the combination of the 50Ohm transmission line and the 100-Ohm pull-down resistor to GND, resulting in the 1.2V amplitude when the signal is high. Refer to this documentation below:

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    Thank you,

    1. This side confirms that the voltage is approximately 1.2V when a "100 ohm" resistor is connected to GND.
    2. Additionally, I would like to inquire what parameters need to be set on the IC for CMOSP's OUT1 and OUT4 to output synchronously.
  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    There are a couple of things to check, all on the User Controls page under the Outputs subsection:

    1. Ensure that the ch1_cmosp_pol and ch4_cmosp_pol are both unchecked.
    2. Ensure that ch1_sync_en and ch4_sync_en are both set to "SYNC Enable" (a field value of 1).
    3. Set and then clear the sync bit.

    Please let me know if you see the P outputs synchronized after these steps.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 10 points

    Hi Kadeem

    We can now synchronize, but the overshoot/undershoot is very obvious. Is there any way to improve it?

    Thanks

  • 0 in reply to Pi-Lun Cheng
    TI__Expert 6325 points

    Hello,

    Kadeem is currently OOO but will return tomorrow.

    For clarity, what is the current schematic from the CDCE6214-Q1 output to the receiver? From what I see, better impedance matching should be able to improve the overshoot, but I am unclear of the current setup so I cannot give any direct recommendations. 

    Best,

    Cris

  • 0 in reply to Cris Kobierowski
    Prodigy 200 points

    Please see the information below

  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    This is likely due to an impedance mismatch on the board.

    This is what we see on the evaluation module when connecting 100Ohms to GND. The first image is the normal swing, and the second is the attenuated swing:

    Try using a slightly smaller or slightly larger resistor than 100Ohms to improve the matching.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    1.Is it mainly due to impedance mismatch? However, it looks more like de-emphasis effect has been applied on the waveform.

    2.We have tried adjusting our equipment to a 50ohm termination match; it appears that we can achieve a square wave form with this setting but anomalies occur when using a 1Mohm termination match.

    3.Currently “determine Jitter” does not meet the 15ps specification; could you please help confirm if there are similar test reports available? (Frequencies: 19.2MHz/26MHz/38.4MHz/52MHz)

  • 0 in reply to Li YuanKan
    Prodigy 200 points

    sorry,deterministic jitter (DJ)

  • 0 in reply to Li YuanKan
    Mastermind 7950 points

    Hi Kadeem,

    Please see below figure and setting file, is there anything need adjustment?

    19.2Mhz

    26Mhz

    38.4MHz

    52Mhz

    Setting file

    設定檔.zip

  • 0 in reply to Jeff YANG
    TI__Mastermind 22810 points

    All,

    The plots in the most recent reply look better, though the DJ in some of these cases is quite a bit higher than I would expect for 19.2MHz and 38.4MHz. I expect that this is due to spurs generated by the fractional division of the PLL. Let me make some modifications and collect data for you by the end of this week. I will also provide the configuration files.

  • 0 in reply to Kadeem Samuel
    TI__Mastermind 22810 points

    Li/Jeff,

    Do you have any specification for the TIE filtering? Usually when this measurement is performed there is a lowpass, highpass, or bandpass filter that is applied to the TIE measurement for calculating the RJ and DJ.

    Using a 12kHz to 20MHz bandpass filter (assumed for all measurements below) and your settings file as is for 52MHz, I am seeing RJ and DJ that meet the specifications.

    For 38.4MHz, I reduce the PLL charge pump current (pll_cp_up) to 100uA to achieve passing DJ, with no other changes - this is largely due to using the PLL in fractional mode rather than integer mode:

    For 26Mhz, I see passing DJ with no changes:

    For 19.2MHz, similar to 38.4MHz, reducing the charge pump current to 100uA results in passing DJ:

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    Are you setting this field? thank you

  • 0 in reply to Li YuanKan
    Prodigy 200 points

    Is it recommended to change all settings to 100uA?(19.2Mhz/26Mhz/38.4Mhz/52Mhz)

    Are there any concerns?

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    Hi Kadeem,

    52Mhz frequency band: The association stipulates that the bandpass is 50KHz-50Mhz

    Is there any other way to overcome the Fail part of DJ parameters?

  • 0 in reply to Li YuanKan
    TI__Expert 6325 points

    Hello,

    Li YuanKan said:
    Are you setting this field? thank you

    Yes, that is the correct field.

    Li YuanKan said:

    Is it recommended to change all settings to 100uA?(19.2Mhz/26Mhz/38.4Mhz/52Mhz)

    Are there any concerns?

    There shouldn't be any issues with that.

    Li YuanKan said:

    52Mhz frequency band: The association stipulates that the bandpass is 50KHz-50Mhz

    Is there any other way to overcome the Fail part of DJ parameters?

    We can retest with this bandpass. Expect the results by Monday.

    Best,

    Cris

  • 0 in reply to Cris Kobierowski
    TI__Expert 6325 points

    Hello,

    We retested the original config you provided but with a CP gain of 100uA and got the following result with the 50k to 50MHz bandpass, which passes the 15ps DJ spec.

    Best,

    Cris

  • 0 in reply to Cris Kobierowski
    Prodigy 200 points

    1.We have adjusted the CP Gain setting to "100uA" and confirmed that "RJ" and "DJ" meet the SPEC standards.

    2.Could you please advise whether the instrument impedance should be set to 50 Ω or 1M Ω during measurement? When we set the instrument to 50 Ω, the voltage amplitude is only 680mV, but RJ and DJ meet the standards. If we set the instrument to 1M Ω, the voltage amplitude can reach 1.2V, but overshoot and undershoot are very severe, causing DJ not to meet the standards.

    3.Under the setting of 50 Ω for the instrument, we still cannot meet the ±150ppm specification for frequency ppm. Could you please suggest any other adjustments that could reduce the ppm value?

  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    The result with 50Ohms should be used for the measurement.

    For increasing/decreasing the frequency, adjust the on-chip load capacitance setting on the Inputs page. This will change the loading on the XTAL, which will cause slight (PPM) adjustment to the frequency. Also ensure that you are using the maximum sampling rate on the oscilloscope.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Prodigy 200 points

    1.  If the instrument is set to 50Ω impedance matching, the voltage will change to 0~680mV. Is this a reasonable setting?

    2.  The SPEC requires VIH to be 1.2V x 0.65 = 0.78V, which cannot be met when set to 50Ω impedance matching.

    3.  When measuring RJ & TJ, is it common practice to set the instrument to 50Ω impedance matching?

  • 0 in reply to Li YuanKan
    TI__Mastermind 22810 points

    Li,

    What we have done in the past is measure the actual VIH and VIL with a high-impedance probe, as the 50Ohm termination of the oscilloscope will function as a resistor divider, halving the swing. The oscilloscope used in the captures that we provided above only supports 50Ohm termination. RJ and TJ are commonly measured with 50Ohm impedance matching.

    Thanks,

    Kadeem