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CDCS504-Q1: About output duty cycle

Atsushi Takahashi
Expert 1415 points
Part Number: CDCS504-Q1
Other Parts Discussed in Thread: CDCE913

Tool/software:

Hi Team,

The customer use CDCS504-Q1 with x4 mode, input frequency = 4MHz and output frequency = 16MHz.

1) Does this device output it with 50% duty, regardless of the input duty cycle?

2) If yes, could you please explain the principle in detail?
For example,
- witch is it sampling the rising or falling edge of the input signal?
- how does this device generate 50% duty output from different duty cycle input?

Best Regards,

  • 0
    TI__Mastermind 22720 points

    Takahashi-san,

    The duty cycle is not production tested. The expectation is that the device will receive an input clock with a (roughly) 50% duty cycle. If the duty cycle is not near 50%, we cannot guarantee that the output will have a 50% duty cycle.

    On other devices (CDCE9xx family), it is rising edge sampling, and the input duty cycle (varied over 20% to 80%) does not impact the output duty cycle.

    Thanks,

    Kadeem

  • 0 in reply to Kadeem Samuel
    Expert 1415 points

    Hi Kadeem-san,

    Thank you for your reply.

    You said:

    On other devices (CDCE9xx family), it is rising edge sampling, and the input duty cycle (varied over 20% to 80%) does not impact the output duty cycle.

    I'm sorry to trouble you, but I would like to know the specifications of CDCS504-Q1, not other devices (CDCE9xx family).

    - Does this product sample at rising edge?

    - What is the input duty range for which 50% duty output is guaranteed?

  • 0 in reply to Atsushi Takahashi
    TI__Mastermind 22720 points

    Takahashi-san,

    I would expect the LVCMOS input stage behavior to be incredibly similar between these devices. However, we cannot guarantee the duty cycle behavior if the input exceeds 45% to 55% duty cycle.

    If the input frequency may truly be lower than this duty cycle range (or higher), my recommendation is to use the CDCE913 for assured operation.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Expert 1415 points

    Hi Kadeem-san,

    Thank you for your reply.

    You said:

    we cannot guarantee the duty cycle behavior if the input exceeds 45% to 55% duty cycle.

    - This is not stated in the datasheet, is it a guaranteed spec?

    You said:

    On other devices (CDCE9xx family), it is rising edge sampling, and the input duty cycle (varied over 20% to 80%) does not impact the output duty cycle.

    - The datasheet of CDCE913 says the input duty cycle is 40% to 60%. Which is correct?

  • 0 in reply to Atsushi Takahashi
    TI__Mastermind 22720 points

    Takahashi-san,

    When we have specifications in the datasheet, they are typically to cover an array of use cases that are defined at product definition, and then validated over the set of operating conditions. The "typical" condition is a 50% duty cycle, but this may be tested over a wider array of duty cycles to ensure proper operation depending on the needs of customer applications that the part is being created for. In the case of the CDCE913, it is production tested over 40% to 60% duty cycle. That does not necessarily mean that the device will immediately fail outside of those bounds, but rather that we cannot guarantee operation outside of those bounds (most often because outside of those bounds is not the "typical use condition" and is not tested).

    Other specifications, though not as common, are guaranteed by design and simulation tested - again depending on the customer needs at the time. The CDCS504 input slew rate is one such specification, where it is checked in the design but not actually production tested (as stated in the datasheet).

    What is the actual input duty cycle that you are targeting here? My recommendation would be to use the CDCE913 in PLL mode to function similarly to a clock multiplier - an evaluation module is also available for this device for testing.

    Thanks,
    Kadeem

  • 0 in reply to Kadeem Samuel
    Expert 1415 points

    Hi Kadeem-san,

    Thank you for your reply.

    The actual input duty cycle that my customer verifies is 30%.

    Under environment of customer system, 16MHz 50% duty outputs from 4MHz input 30% duty with x4 mode.

    However, since the datasheet does not state input duty requirements, I'd like to confirm whether it is guaranteed behavior or not, so I asked.

  • 0 in reply to Atsushi Takahashi
    TI__Mastermind 22720 points

    Takahashi-san,

    While we cannot guarantee the behavior, I expect from my bench testing that this should be alright with CDCE913 specifically.

    Thanks,

    Kadeem