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LMK04832-SP: OSCin input from a HCMOS driver

Arooj Aslam
Prodigy 50 points
Part Number: LMK04832-SP
Other Parts Discussed in Thread: LMK04832

Tool/software:

I am using the LMK04832 chip in distribution mode and using the OSCout pins as buffered outputs of the OSCin pin.

We have a 100 Mhz HCMOS output reference clock (EX-219 from Microsemi, datasheet EX-219 | Microchip Technology) and our voltage supply for the oscillator and the LMK is 3.3V. We are using OSCin as a single ended input, and the OSCin negative pin is AC-coupled to ground.

In particular I am concerned about the voltage levels being within the specs described in section 6.5.

We are using the oscillator with an HCMOS output and the specs show Vol = 0.1*Vs = 0.1*3.3V = .33V, and Voh = .9*3.3V = 2.97V. Below the input specs for OSCin show the Vpp to be from .2V to 2.4V, so I am concerned we are going above the maximum limit for a single ended input.

  • 0
    TI__Mastermind 24051 points

    Hello Arooj, 
    According to what you sent, yes you would be operating outside the recommended range for OSCin single ended. 
    You need to reduce the swing. 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 50 points

    Thank you so much. I added a 66.5 ohm resistor to reduce the voltage swing. So now we will be swinging from 0.2V to 1.7V. Will that allow enough of a noise margin between the low and high voltages? The range just says 0.3 to 2.4V max, but I wasn't sure if we need to be closer to 2.4V?

  • 0 in reply to Arooj Aslam
    TI__Expert 5320 points

    Hi Arooj,

    Please see the screenshot from the datasheet below:

    The high end of your swing needs to be increased above 2V, but your low end needs to stay between 0V and 0.4V. A smaller resistor (perhaps a 50 ohm?) would be the best choice to reduce the swing while keeping it within a tolerable range.

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 50 points

    Is that requirement also true for the OSCin pin? The reason we wanted to skew the voltage drop is because we already have a 50 ohm resistor on the board that is an 0402 (50mW) resistor that would fail our derating requirements if we put more than 1.6V on it...

  • 0 in reply to Arooj Aslam
    TI__Expert 5320 points

    Hi Arooj, 

    My apologies, I was reading the specifications for the CLKinX inputs. 

    Your swing should be fine, but if you are AC coupling your OSCin* pin to GND, you also need to AC couple your single-ended signal going into OSCin. That way, the OSCin* pin will be at a known state that is roughly the halfway point of the input signal, and given that your swing (1.5 Vpp if I understand correctly) falls within a tolerable range, you should be fine.

    It is worth noting that this should work with your previous setup. AC coupling your signal with a ~2.6Vpp swing should mean that the maximum voltage comes out to ~1.3Vpp, which is acceptable for the OSCin inputs. 

    If you have to DC couple your input signal, then you will need to bias your OSCin* pin to half of your input level. If your signal goes from 0.2V to 1.7V, OSCin* will need to be biased to 0.95V. 

    Thanks,

    Michael

  • 0 in reply to Michael Srinivasan
    Prodigy 50 points

    So we currently have our circuit matching this circuit shown in the data sheet for a sinewave input, even though ours is a HCMOS input that goes from 0 to 3.3V.

    We are thinking to add a 66.5 ohm resistor in series with the output of the clock source to create the voltage divider that will bring the voltage going to the LMK input to be from 0V to 1.5V.

    We have AC coupled both inputs including the one to ground. 

    Would you be able to explain a little more how the internal biasing works? Is there another resistor divider network internally that reduces the input voltage, or does it just raise the DC level to create a common mode voltage at the halfway point?

    Mainly, I don't understand this statement: "

    It is worth noting that this should work with your previous setup. AC coupling your signal with a ~2.6Vpp swing should mean that the maximum voltage comes out to ~1.3Vpp, which is acceptable for the OSCin inputs. "

    If our input voltage from the clock source is 0 to 3.3V, then due the internal bias we are actually inputting 0 to 1.65 (half of 3.3V)? Or am I misunderstanding?

  • +1 in reply to Arooj Aslam
    TI__Expert 5320 points

    Hi Arooj,

    The internal biasing works by raising the DC level to the CM voltage, as you said. Each of the inputs will be internally biased, so you should AC couple your inputs. When that happens, any DC offset is removed from your signal (at least until it is re-biased by the input pin). It will have the same amplitude but its offset will become 0V. So if you have a 0V to 3.3V signal, AC coupling it will make it swing from -1.65V to 1.65V. It will be re-biased to the common mode voltage, so that should mean the signal swings from -.45V to 2.85V. I misspoke earlier in saying "It is worth noting that this should work with your previous setup. AC coupling your signal with a ~2.6Vpp swing should mean that the maximum voltage comes out to ~1.3Vpp, which is acceptable for the OSCin inputs". The swing exceeds the acceptable maximum of 2.4Vpp.

    However, with your 66.5 Ohm resistor instantiated, you should have no issues, so long as you AC couple the signal with the reduced swing. You are AC coupling your OSCin* pin to GND, and your OSCin pin will need to be AC coupled as well.

    I will be out on vacation the rest of this week and next week, so I will include other AEs to help you.

    Thanks,

    Michael

  • +1 in reply to Michael Srinivasan
    Prodigy 50 points

    Thank you so much for all your help! I think this answers all my questions for now!

    Have a fun vacation!