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LMK04832: SYSREF as REF IN or FB

new2day
Expert 1920 points
Part Number: LMK04832

Tool/software:

LMK04832 supports two VCO with range at VCO0 2440 ~ 2580 MHz and VCO1 2945 ~ 3255 MHz.

In JESD204B, SYSREF is normally < 10MHz with certain division requirement to the device clock and sampling clock and so on. 

How to set up a single loop 0-delay mode with REF IN  is less than 10MHz or using SYSREF as FB. 

When the REF IN or FB is less than 10MHz, VCO Cal Frequency will not be the same as VCO Freq. Which is causing error. 

I have play with TICS Pro with no success. 

Was it feasible? Thank you.

  • 0
    TI__Mastermind 24051 points

    Hi New2day, 
    Can you provide me with a block diagram/clock tree of what you're trying to implement here? 
    When you implement ZDM you will have a PLL status message to help you determine if device is locked & or if you're using incorrect divider value. 
    Take the following as an example: 

    Since the N divider is 2 - the output of the N divider is 61.44MHz & thus PLL2 isn't locked. 
    The N divider must be set equal to 1. 
    If set to 1 you get a message - PLL2 locked. 



    Best Regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Expert 1920 points

    Hi Vicente,

    I like to configure LMK04832 in single loop 0-delay mode.

    The Device Clock outputs can be from 100MHz to 400MHz and SYSREF can be from 1.25 to 7.8125 MHz according to the Device Clock.

    I like to check was it possible to use SYSREF as REF CLK IN or FB CLK to the N divider path - it seems yes according to SNAA2019. 

    How to do so if it's feasible. 

    I could not get VCO frequency right if doing so from TICS Pro. Thank you.

  • 0 in reply to new2day
    TI__Expert 5320 points

    Hello,

    I am a bit confused by your proposed solution. If I understand correctly, you want to re-clock your SYSREF signal along your distribution path - which is a feasible solution. Your input to the CLKin0 pin may be sent to the SYSREF_MUX, which can then distribute it as a SYSREF signal. 

    It is possible to use SYSREF as a FB CLK for the N divider path, but it is important to note that you must either have a SYSREF frequency large enough to divide down into the PFD frequency, or you must use a low PFD frequency that accounts for the input to the N divider. This will either result in cross-talk or a poor phase noise performance. 

    Furthermore, it is important to mention that SYSREF signals are only output upon a SYNC event. Until that occurs, if you use SYSREF as the input to the FB_MUX, your PLL will lose lock (this to say, you are going to lose lock at the start of operation). 

    A clock tree or functional block diagram would be helpful to provide any further assistance.

    Thanks,

    Michael