LMK04828BEVM: PLL1 lock fails when generating DAC Ref Clk from SFP recovered clk in clk104 RF add on card

Vaishnavi Adurti

Part Number: LMK04828BEVM

Tool/software:

Hi,

As a follow up to our earlier query, when we use the ethernet recovered clock from another ZCU208 board for clkin2 input, PLL locks successfully.

However when we use the ethernet recovered clock from our custom board based on ZCU9EG FPGA Part having GTH transceivers and use it as input to clkin2 input of ZCU208, PLL lock fails in LMK.

What could be the reason, is there any difference in the clocks recovered from GTY and GTH, and if the signal in second scenario is of high jitter, how can that be countered in LMK configuration to get successful PLL lock.

Looking forward to your reply, Thank you

7 months ago

0 Connor Lewis 7 months ago

TI__Genius 12570 points

Hi Vaishnavi,

Adding a link to your previous thread here for reference: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1424537/lmk04828bevm-pll1-lock-fails-when-generating-dac-ref-clk-from-sfp-recovered-clk-in-clk104-rf-add-on-card

Are there any differences in the signal amplitude, common mode, or slew rate with the recovered clock from the ZCU208 board compared to the ZCU9EG board? It would be good to verify that the input requirements below are being met.

If the input has high jitter (especially high close in phase noise), then if the loop filter bandwidth is too narrow it could be difficult for the VCO to track the noise and stay locked to the reference. You could try using PLLatinum Sim to check the bandwidth of the filter and calculate the values for a filter with a wider bandwidth.

Regards,

Connor

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LMK04828BEVM: PLL1 lock fails when generating DAC Ref Clk from SFP recovered clk in clk104 RF add on card