LMK04828: LMK04828

Hi Salman,

First of all, I want to note that your phase detector frequency for your first PLL is very low, and will result in worsened phase noise performance, as a result. However, your on board VCXO has a frequency that is a multiple of the 10.23 MHz reference. As a result, you should be able to set your phase detector frequency to 10.23 MHz. When you set this value to be your PFD1, are you still only able to achieve lock with a 10 MHz input?

Thanks,

Michael

Hi Michael,

I have modified PLL1 phase detector frequency to 10.23MHz but still lock happens with 10MHz input only.

Regards

Salman

Hi Salman, 

Thank you for sharing that information with me. I am currently on business travel, but should be back to my home office tomorrow afternoon. I will see if I can replicate your issue.

Thanks,

Michael

Hi Michael,

Thank you for the response. 

This issue is in top priority for us. Kindly support us to resolve the issue at the earliest.

Regards

Salman

Hi Salman,

I have just returned to office. I will see if I can replicate the issue and get back to you by the end of the day.

Thanks,

Michael

Hi Salman,

I want to preface by saying that I was not able to test your exact values in lab. Our LMK04828 evaluation modules come pre-populated with a 122.88 MHz VCXO. However, I was able to use the scaling factor (~0.75) that related 122.88 MHz and your VCXO frequency of 163.68 MHz in order to scale down all of the values you used so that I could achieve lock while using the same R and N divider values (I was not as worried about your PLL2, as you stated it is already generating the correct output, which it should be doing so long as the VCXO is driving it). 

When I used this configuration, I found that both PLLs were locking, and PLL1 would lose lock if I changed the input frequency at all. I tried the scaled down version of 10 MHz - 7.51 MHz - and found that PLL1 lost lock. 

In conclusion, I was not able to replicate your issue on my board. Would you be able to share the schematic of the board you are using? The fact that PLL1 will only lock to an input frequency of 10 MHz makes me suspicious that the VCXO on the board is a multiple of 10 MHz. Additionally, can you tell me if PLL2 ever loses lock?

Thanks,

Michael

Hi Michael,

I have attached user guide of the board.

In the board, it is mentioned VXCO is 160MHz, then my configuration of 163.68 is not correct? It generates only 160MHz? 

If so, please let me know how to go ahead to achieve 1.96416GHz sampling frequency. 

Regarding PLL2, it is getting locked always.clk104 user guide.pdf

Regards

Salman

Hi Michael,

Board rework is required for single loop mode? 

If not, Please guide how single loop mode configuration to be done to achieve 1.96416GHz.

regards

Salman

Hi Salman, 

As you can see in Figure 21 in the datasheet (which I have attached below), you can only use single-loop mode by inputting the signal into OSCin. Currently, the signal which you will need to input to OSCin is being input to CLKin0. You will have to route that signal into OSCin in order to have proper single loop functionality.

Thanks,

Michael

Hi Michael,

Thank you for sharing the information. As per datasheet of CLK104, it is not possible to feed external input to OSCIn. 

Kindly suggest, is there any other way to generate reference clock for 1.96416GHz with 10MHz input instead of 10.23MHz. 

 Also, whether Set Distribution mode help us to achieve desired reference clock? there also I see it takes input from CLKIn1, which may not work in this card?

There are LMX2594 PLL chips for ADC and DAC in CLK104 card, whether this will help?

regards

Salman

Hi Salman,

There is a way to generate a 1.96416 GHz reference clock with a 10 MHz input instead of a 10.23 MHz. Be forewarned that this configuration will have a degraded noise performance due to the high value that the PLL2 N Divider has to be set to. I have attached a configuration that outputs a SYSREF signal with a frequency of 7.6725 MHz. 

196416_sampl.tcs

Thanks,

Michael

Hi Salman,

There is actually a method for calculating the PFD frequency for a given reference frequency and oscillator frequency. The PFD frequency needs to be the greatest common factor of those two frequencies, and using that value will ensure an integer multiplicative relationship between all of the values.

Thanks,

Michael