Tool/software:
Hello,
I am using LMX2572LP in a design for a couple of PLLs. They are working fine in the 800MHz-1000MHz range which is our desired range.
Fractional mode is needed for the steps in this range.
Now we want to get it working with an external SYNC pin input to trigger the sync.
As given in the datasheet this puts us in Category 3 of sync.
- fOSC is within the range (100 MHz)
- OSC_2X, MULT are both not set
- Set N = N'/2 is not possible as this takes the value below 20, so instead I am setting PLL_R = 2 to compensate for the extra divide by 2 in the fVCO path
- Since now the pFD is half of before I changed FCAL_HPFD_ADJ accordingly from 2 to 1
- All registers programmed with VCO_PHASE_SYNC_EN=1 in R0
- However, I am not getting lock beyond a few frequencies, whereas earlier without VCO_PHASE_SYNC_EN the entire frequency range locked for both of our PLLs.
I am not sure if what I have done above using PLL_R = 2 (instead of = 1 without VCO_PHASE_SYNC_EN) is correct?
I could not think of any other method to keep the new N value within range.
I checked by using TICSPro simulation and it confirmed same settings as I have used.
Please advise.
Thanks,
Arun