• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 22 subscribers
  • Views 350 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04832: Output Clocks Not Phase Aligned after adjusting Output Clock Divider

LMK04832: Output Clocks Not Phase Aligned with Input Clock in 0-delay Mode

Grant Skeels
Prodigy 45 points
Part Number: LMK04832


Tool/software:

Hi All,

Utilizing an LMK04832 we are attempting to edge align the CLKout, External VCXO (OscIn for PLL2), and ClkInX. After reading the datasheet, we believe 0-delay is the best method to get this done. We have attempted to set the PLL into dual-loop 0-delay nested + cascaded without any luck. 

We have attached our TICS PRO configuration in case we are missing a config. We have measured a 30ns offset between ClkInX (10MHz) and ClkOut (10MHz). We are aware that in 0-delay mode, there is a deterministic phase relationship with VCXO, ClkIn, and output Clocks and they may not be edge aligned.

We are looking for a sync, PLL R divider sync, or offset we can apply to edge align our ClkInX, OscIn, and ClkOut. 

Thank you for the assistance,

Grant

LMK04832_NC_IDL_ODL.tcs

  • +1
    TI__Mastermind 29542 points

    Hello Grant, 
    Currently output-to-input phase deterministic is not possible with your configuration given N/R does not reduce to '1'. 
    If R does not equal 1 that many times is not a problem given, we have PLL R divider resets, but we do not have resets for the N divider. 
    We have an appnote you can refer to for more info. 
    You can use the Sysref divider as the feedback clock (10MHz) and this will also ensure the N divider is also equal to 1 for PLL1. 
    You would also change the R divider from 2 to 1. which ensures N/R = 1. 
    Otherwise, you could reduce the output clock that is feedback from 125MHz to 10MHz (while at the same take doubling the Pfd from 5MHz to 10MHz) to also reduce N/R from the current ratio to reduce to '1' instead. 
    Best regards, 

    Vicente 

    Synchronization of Multiple LMK0482x Devices

  • 0 in reply to vicente flores prado
    Prodigy 45 points

    Thanks for your response, sounds like it not possible given our HW limitations.

    Is there a way to align all the CLKout of the LMK04832 without glitching the output? One of the output drives our FPGA, and glitching the clock during a SYNC causes our system to panic. We attempted to block it by setting the sync disable bit true (Reg 0x144 = 0x10) but the FPGA clock never aligned with the other "Synced" output clocks.

    Thanks,

    Grant

  • 0 in reply to Grant Skeels
    TI__Mastermind 29542 points

    Hello Grant, 
    Unfortunately, that is not possible during a sync event. 

    Best regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    Prodigy 45 points

    Hi Vicente,

    Thanks for the quick reply. Is there a way to align the output clocks without a sync event?

    Thanks,

    Grant

  • 0 in reply to Grant Skeels
    TI__Mastermind 29542 points

    Hi Grant, 
    Unfortunately, no. 
    A sync event is required to reset the output dividers so they share a common rising edge from the clock distribution path so the ouputs can be edge aligned. 

    Best regards, 

    Vicente