Other Parts Discussed in Thread: LMK5B33414
Tool/software:
Hello,
I am trying to design the following:
Inputs:
- RefIN0 = "dirty" 1-PPS from GPS receiver
- RefIN1 = nothing
- OCXO = 100MHz disciplined OCXO
Outputs that must be phase aligned (2 of each: 1 LVDS, 1 LVPECL/HSDS 800 mV 1 V):
- 1 PPS (ZDM from PPS input if possible)
- 10 MHz
- 100 MHz
- 1 GHz
Other Outputs:
- Configurable clock rate, say it is 156.25 MHz for now, it can be phase aligned but not a hard requirement
I was reading the datasheet and believe that I want the cascaded DPLL operation if I want all of the outputs phase aligned and synchronized to the input? I have attempted testing this and could not get different APLL outputs to phase align with each other, but outputs from the same APLL seem to work fine. I am relatively new to this part, so please correct me if I am wrong.
Lastly, I am using a seperate SPI driver to test this, could you point me to important STATUS registers to monitor throughout my programming and testing, especially regarding DPLL/APLL lock status and Input reference detection.
Thanks in advance.
