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Original question:

LMK04832: LMK04832: LMK04832 PECL Output [DC Termination Versus AC Termination]

LMK04832: About LMK04832(Nested 0-Delay Dual Loop Mode) Locking process

APPLO ZHANG
Intellectual 515 points
Part Number: LMK04832

Tool/software:

Hi，TI Team:

I would like to know the detailed locking process of PLL1/2 in Nested 0-Delay Dual Loop Mode.

How long does it take for PLL1/2 to lock (the loop filter bandwidth is shown in the figure)?

During the locking process, does the chip have any output, and does the output divider take effect?

Thanks!

  • 0
    TI__Expert 8830 points

    Hi Applo,

    Sorry for the delay.

    The locking process for PLL1/2 is dependent upon the respective values of the phase detectors and the PLLx_DLD_CNT. 

    PLLx_DLD_CNT is a user specified number that determines how many cycles in which lock must be detected until lock detect is asserted by the device. 

    The minimum lock time can be calculated by PLLx_DLD_CNT / phase detector frequency.

    You can also output the lock detect status on the Status_LD1 or Status_LD2 pins - these are the only outputs that can indicate the state of lock. The output divider will take effect even if the PLLs are not locked.

    Thanks,

    Michael