CDCM6208: The phase noise of the clock source is not clean at 10K.

Wen,

Do you have the phase noise of the input clock that you can provide while we debug this?

Thanks,

Kadeem

20250909.docx

Please   refer to the document. this is our test  data, thanks

Wen,

From bench testing with your configuration, I found that the 10kHz offset cannot be optimized much further using the registers. That said, altering the external loop filter values was able to change this drastically.

I have two questions:

1. Can you confirm the external loop filter values being used on your board? 

2. From my bench testing, I found that I was able to reduce the noise at the 10kHz offset, but at the expense of the overall jitter value. Which is valued more? I can still provide several options and captures for each, but I would like to better understand the priority here. 

Best,

Cris

250915.docx

1,our C1=470P,R2=560,C2=100n

2,We can modify the resistors and capacitors around the CDCM6208.

3,If possible, please provide a compromise solution between the overall noise level and the 10 kHz noise peak. We can modify registers or adjust the resistors and capacitors on the board.

thanks!