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LMK5C22212A: Design Inquiry

Abhishek Manoj
Intellectual 555 points

Part Number: LMK5C22212A

Hi Team,

I'm planning to use LMK5C22212ARGCT in my board.

The clock tree of the board is shared below.(Note only check the output clock type and frequencies, the output pins connected to IC may be different, schematics will be the correct one connected.)

I want 7 LVDS outs and 3 CMOS outs. The jitter requirement is >100fs.

The IC input is only through OXCO crystal (OX-221-9102-49M152 - 49MHz).

image.png

The schematics of the clock IC is also attached with it.

LMK5C22212ARGCT.pdf 

Please review and provide the feedbacks and also please address some queries.

1.GPIO,SDA, SCLK what is the IO level?
2.For LVCMOS 1.8V output is there any hardware wise changes need to differentiate 2.5V and 1.8V output
3.My OXCO is 49MHz OX-221-9102-49M152, is it okay for my design.
4.I'm using only OXCO input for the IC, IN0 and IN1 can be left NC?
5.What is the 3.3V total power consumption for my circuit as in datasheet current for 256MHz LVDS out on all clock outs is only mentioned?

6.Any suggestion is there to connect my outputs as per my jitter requirement.

 

Regards,

Abhishek

 

  • 0
    Intellectual 555 points

    Hi team,

    Please provide the current consumption by 3.3V rail for the above configuration.

    Regards,
    Abhishek

  • 0 in reply to Abhishek Manoj
    TI__Genius 17025 points

    Hi Abhishek,

    Please allow us this week to check this.

    Kindly,

    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 555 points

    Hi Jennifer

    Please provide the update by today because we want to confirm this design to our end customer.

    Regards,

    Abhishek

  • 0
    TI__Genius 17025 points

    Hi Abhishek,

    1.GPIO,SDA, SCLK what is the IO level?

    --> Please refer to the datasheet. VDD is 3.3V.


    2.For LVCMOS 1.8V output is there any hardware wise changes need to differentiate 2.5V and 1.8V output

    --> Nothing for HW. The differentiation occurs by register configuration.


    3.My OXCO is 49MHz OX-221-9102-49M152, is it okay for my design.

    --> No concerns


    4.I'm using only OXCO input for the IC, IN0 and IN1 can be left NC?

    --> Yes. Disable the DPLL in the register configuration to use the device in APLL only mode. The DPLL must be enabled if using IN0 or IN1.


    5.What is the 3.3V total power consumption for my circuit as in datasheet current for 256MHz LVDS out on all clock outs is only mentioned?

    --> I don't have the power consumption data readily available for your exact configuration. However, you may use this data sheet spec for guidance (about 1A since both the BAW APLL and APLL2 are enabled).

    For the schematic review:

    -->LFx must follow data sheet recommendation.

     

    --> If EMI is a concern, I recommend enabling OUT1_N and routing the OUT1_P and OUT1_N LVCMOS signals as tightly coupled traces to reduce emission.

    Kindly,
    Jennifer

  • 0 in reply to Jennifer Bernal
    Intellectual 555 points

    Hi Jennifer,

    Thanks for the clarifications.

    1.Disable the DPLL in the register configuration to use the device in APLL only mode. The DPLL must be enabled if using IN0 or IN1. It is done in TICS pro tool or any hardware changes?

    2.LFx must follow data sheet recommendation.

    LF1 - 470nF and LF2-100nF. Is my understanding correct.

    3.Other than this the schematic is fine. I had just changed the output pins. Kindly check the updated schematics with the feedback updated.

    LMK5C22212ARGCT_updated.pdf

    Regards,

    Abhishek

  • 0 in reply to Abhishek Manoj
    TI__Genius 17025 points

    Hi Abhishek,

    1. Correct. The DPLL configuration is a SW change, not HW.

    2. and 3. Looks good now.

    Kindly,

    Jennifer