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LMK5B33216EVM: Sync issues across output pairs

Thomas Gayagoy
Prodigy 85 points

Part Number: LMK5B33216EVM

Hello,

We are having trouble syncing across channel pairs and we are wondering if we are setting our TICsPro / register configuration settings incorrectly.

More specifically, we are aiming to syncronize a pulse on output channels 10 , 11 , 12 with an input sysref trigger (trying trigger with both GPIO 0 and software).

It seems like with our current configuration, we can get 10 and 11 to line up when scoping the lines, but 12 seems to drift when comparing to the other 2 outputs. 

Attached is our current configuration for the device.

LMK5B_tics_pro_v11.tcs 

Thank you,

Tom

  • 0
    TI__Expert 3285 points

    Hi Tom,

    Could you try with resampled SYSREF request through these settings:

    You could toggle SYSREF_REQ_SW = 0/1 or GPIOx to request the pulse. See if that helps.

    Best,

    Riley

  • 0 in reply to Riley Nguyen
    Prodigy 85 points

    Hi Riley,

    Thanks for the help!

    We are able to trigger the pulse on the outputs using the resampled scheme you suggested. Unfortunately, we are still seeing some inconsistency / desync between channels 10 and 12, similar to the settings we were using before.

    Thanks again,

    Tom

  • 0 in reply to Thomas Gayagoy
    TI__Expert 3285 points

    Hi Tom,

    Could you share screenshot of the drifting? Perhaps oscope shot?

    Best,
    Riley

  • 0 in reply to Riley Nguyen
    Prodigy 85 points

    Of course. Please see below.

    All captures using envelope mode, so it is a combined result of several syref trigger attempts.

    Out 10 = yellow, Out 11 = blue, envelope capture with sending several sysref triggers, looks like it lines up for the most part.

     

    Out 10 = yellow, Out 12 = blue, envelope capture with sending several sysref triggers, Out 12 doesn't seems to consistently misalign, it will hop around on successive sysref triggers

    Out 10 = yellow, out 12 = blue, envelope capture, no analog delay

    Thanks,

    Tom

  • +1 in reply to Thomas Gayagoy
    TI__Expert 3285 points

    Hi Tom,

    I checked OUT12 clock and it is out of phase upon syncing compared to OUT10-11. This is because we're using PLL3_PRI_DIV = 1 and bypassing CHDIV to SYSREF while the max frequency of input to SYSREF path is 1.25 GHz.

    Try changing OUT_x_y_CH_DIV = 5 and OUT_x_y_SR_DIV = 2 to achieve SYSREF clock on OUT10-11-12 with OUT_x_y_SR_CH_DIV_BYPASS = CHDIV

    This would make OUT13 become 500 MHz so you might want to change OUT14 divider to get 250 MHz.

    Hope this help.

    Best,
    Riley

  • 0 in reply to Riley Nguyen
    Prodigy 85 points

    Hi Riley,

    The bypass settings and matching the divider settings on the chdiv and sysref seems to get us aligned on all 3 of the sysref channels we were targeting (10/11/12). 

    Thanks again for the help!

    Tom