LMK04832: LMK04832 sync

Hello,

Do you have a method of SYNC generation? If so, then you can simply route that to the SYNC input of the LMK04832. If not, you can trigger a SYNC event using the SYNC_POL register. This will align any output channels not affected by the corresponding SYNC_DISx bits and generate the SYSREF outputs.

Thanks,

Michael

I have two FPGAs, and their outputs are SYNC signals. I want to perform an AND operation on these signals and then output multiple SYNC signals. I mainly want to know if there are any recommended models for this AND operation, as shown in the block diagram.

Hello,

Ideally, you will want a fast operating AND gate, which can be found at the following link: https://www.ti.com/product-category/logic-voltage-translation/logic-gates/and-gates/products.html#1512=AUC& . This will AND the incoming signals, and can generate multiple outputs.

Thanks,

Michael

Hi

    I saw SN74AUC1G08,The introduction mentions that it supports a maximum rate of 250MHz, but its datasheet does not contain any information about the rate. Could you please provide relevant materials for reference?

Hello,

Let me loop in the appropriate product line.

Thanks,

Michael