CDCM7005: application question

Hi Imi-san,

Is customer switching over PRI_REF and SEC_REF automatically or manually? 

From the datasheet section 9.3.2.1: "The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD (phase frequency detect) are inside a predefined lock detect window, or if no frequency offset appears, for a pre-defined number of successive clock cycles. The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window or if a frequency offset appears."

You can reference this E2E thread for manual clock reference selection

Best,

Sandra 

Hi Sandra,

The customer issue is PLL_LOCK=High even though PRI_REF clock is unlocked against VCXO_IN clock. So I think this is the condition that clocks are outside of lock detect window in PFD.

This is why we are asked if we can see the other PLL_LOCK=High condition.

regards,

Imi-san,

Can you share with me customer schematic over the email thread? 

Can you also share the state of the /HOLD pin and its programming? This may cause similar issues as to what you're describing, check figure 21 of the datasheet 

Best,

Sandra