LMK04832: AMD RFSOC and LMK04832/LMX2594 sysref configuration

Hi Jose,

Would you be able to share your configuration as a .tcs file? This can be done in TICS Pro using File -> Save. 

Furthermore, I notice all of your SYNC_DISx bits are set - can you try setting those to 0? Having those set means that a SYNC event will not phase align the corresponding outputs. I would also recommend setting SYNC_1SHOT_EN = 1, that way, your SYNC pin/functionality becomes edge sensitive, as opposed to level sensitive.

Thanks,

Michael

Thank you for your reply Michael,

Do you mean set SYNC_DISSYSREF=0 and SYNC_DISx=0 in the tcs file or at the end of the sequence to align?

My original tcs file:

sysref_prueba.tcs

I have done 2 new tcs files with your changes and I have tried them with my original sequence to align:

tcs1: SYNC_DISSYSREF=0, SYNC_DISx=0, SYNC_1SHOT_EN=1
tcs2: SYNC_DISSYSREF=1, SYNC_DISx=1, SYNC_1SHOT_EN=1

And I have the same issue, there is no change versus my original tcs.

And If I use tcs1 and tcs2 with this sequence:

SYSREF_CLR=1
SYNC_DISSYSREF=0 SYNC_DISx=0
SYNC_POL=0
SYNC_POL=1
SYNC_POL=0
SYSREF_CLR=0
SYSREF_MUX=0x03

I don’t have a right sysref in the LMK04832 output, the baremetal gives error and I don’t have 8mhz in the output.

By other side, I don’t have signal in SYNC/SYSREF_REQ pin of my lmk04832, always to low level.

In my board there are 4x LMX2594 and 2 of them generate the sample clock for DAC and ADC of my RFOSC, and I have seen they receive 4 sync pin from LMK04832.

Do I need use that pins to sinchronizate the LMX2594 outputs?

I have seen in my tcs I have clock1 and clock 3 (SYNC_PIN to LMX2594) like LVDS so perhaps I need to set these outputs to CMOS(Norm/Norm)

Hi Jose,

The SYSREF_CLR bit must be cleared (SYSREF_CLR=0) before the SYSREF outputs can be generated. 

José Luis Munoz said:

Do I need use that pins to sinchronizate the LMX2594 outputs?

You can use these outputs to synchronize the LMX2594 outputs, with the outputs configured to issue a rising edge/pulse to the LMX2594 SYNC inputs (ideally, this can be done with SYSREF Pulser mode).

Thanks,

Michael

Hi Michael,

I have been doing some test

This is my LMK04832 tcs file, with normal sync, sysref_pd=0...

sysref_ti.tcs

I don't understand your reply about when I need to clear SYSREF_CLR=0, what sequence is right? 1 or 2?

1) I read in datasheet:
SYSREF_CLR=1
SYNC_DISSYSREF=0 & SYNC_DISx=0
SYNC_POL=1
SYNC_POL=0
SYSREF_CLR=0
SYSREF_MUX=0x03

2) But in e2e.ti.com/.../lmk04832-sysref-synchronization I read this one:

SYNC_DISSYSREF=0 & SYNC_DISx=0
SYSREF_CLR=1
SYSREF_CLR=0
SYNC_POL=1
SYNC_POL=0
SYSREF_MUX=0x03

By other side, LMX2594 tells me I have Cat1 Sync and I don't need external sync pin to align outputs

LMX2594_384_ 6912.tcs

LMK04832 generates clkref (384mhz) and sysref clock (8mhz) for my FPGA, and reference clocks (384Mhz) for LMX2594 who generates the samples frequency (6912mhz) for RFSOC DACs

The issue is all DAC inside tiles are align between them always, but there is a phase shift between tiles, and not always is the same phase shift, depend on the system init

The steps I do are:
I progam all LMK04832 registers
I write the sequence in LMK04832
I progam all LMX2594 registers
I calibrate LMX2594

I'm grateful for your help

Regards