CDCM6208: Regarding CDCM6208 Clock Generator Suitability

Hi Shirke,

Please share the requirements of these devices so that we can comment on that. 

Alternatively you can comment on the Data Converters forum to gain information on their requirements. 

Best,

Sandra 

Hi Sandra,
Thank you for your response.

We are currently designing an 8-channel ultrasound device prototype and require an ultra-low-power, low-jitter clock generator capable of driving all necessary clocks for our modules from a single source. The primary components in our design are the AFE5809, TX08D, and FPGA.

We would like to confirm whether the CDCM6208 has the capability to provide the required clock signals for all these modules from a single source.

I have already submitted a support request on the Data Converters forum but have not yet received a response. For your reference, I have included the link to the forum ticket below: AFE5809: Clarification Required on ADC Clock Configuration for AFE5809 Ultrasound Prototype 

Could you please review our requirements and advise on a suitable solution?

Best regards,
Harsh

Hi Harsh,

Thanks for the added information, we have a full clock tree for medical ultrasound front end unit listed in this app note that you can share with the customer 

https://www.ti.com/lit/an/snaa311a/snaa311a.pdf

Additionally for the back end unit my understanding is that they need PCIe clocking which they can use the LMKDBxxxx family. 

Let me know if there are any additional questions

Best,

Sandra 

Dear Sandra,

Thank you for your response.

Within the LMKDBxxxx family, could you please assist us in designing a clock generator circuit that meets our requirements?

For the AFE5809, we have decided to operate in TGC mode rather than CW mode. Based on this configuration, we would appreciate your guidance in generating suitable clock signals for the AFE5809, TX08D, and the FPGA.

Best regards,

Harsh

HI Harsh,

 The LMKDBxxxx is a PCIe buffer family.

The app note I have shared earlier highlights the clock tree based on the requirements of front end unit for ultrasound.  

As i am not familiar with the requirements of these devices, you will have to share with me the clock requirements (number of channels and their respective frequencies and output formats, jitter requirements and phase noise requirements) so that I can recommend a clock tree 

Best,

Sandra  

Hi Sandra,

Thank you for your clarification regarding the LMKDBxxxx PCIe buffer family.

We are designing an 8-channel ultrasound system, and the clock requirements for the front-end devices are as follows:

1. AFE5809 (8-Channel ADC Front End)

• Number of Devices: 1 (8 receive channels)

• ADC Sampling Clock: 10 MHz to 65 MHz

• Clock Input Type: LVDS differential preferred

• Jitter Requirement: < 1 ps RMS (to maintain ADC SNR performance)

• Phase Noise: Low close-in phase noise required for imaging quality

2. TX08D (Transmit Section)

• Clock Type: LVDS differential

• Frequency: Up to 250 MHz (maximum)

• Jitter Requirement: Low jitter for precise transmit timing alignment

3. Cyclone 5E FPGA

• System Clock: 50–100 MHz (flexible)

• Reference Clock: Clean differential clock preferred for PLL stability

• Jitter Requirement: Low jitter recommended for reliable LVDS data capture

Based on the above requirements, kindly recommend a suitable clock tree architecture for this 8-channel ultrasound system.

Best regards,
Harsh Shirke

Hi Harsh,

I'll get back to you by the end of the week 

Best,

Sandra