Part Number: LMK04828
Hello TI Support Team,
I am designing a clock tree using the LMK04828 and have a question regarding the CLKin input requirements (used for JESD204B SYSREF) when the driving source is temporarily disabled.
[System Setup]
I am driving the LMK04828 CLKin0 port with an external LVDS fanout buffer (NB3L8504S).
The signal is DC-coupled with a 100-ohm differential termination resistor placed close to the LMK04828 input pins.
The buffer has an Output Enable (OE) pin. When the OE pin is pulled LOW, the LVDS outputs go into a High-Impedance (High-Z) state.
[My Inquiry]
In the LMK04828 datasheet (Section 10.7 Do's and Don'ts), it states: "Unused Clock Inputs: unused clock inputs can be left floating."
However, my CLKin is not physically "unused" or completely unconnected; it is dynamically turned off (High-Z) via the buffer's OE pin while still connected to traces and the 100-ohm termination. In this High-Z state, the differential voltage ($V_{ID}$) across the 100-ohm resistor essentially becomes 0V.
Could you please clarify the following based on the datasheet specifications?
Risk of False Triggering (Chattering): Since V_ID = 0V falls into the threshold region of the receiver and violates the minimum |V_ID| specification, will leaving the buffer in High-Z cause chattering or false SYSREF triggering due to ambient noise picked up by the traces?
Fail-Safe Biasing Requirement: To prevent any metastable state, is it officially recommended to add an external fail-safe bias network (e.g., 1k-ohm pull-down on the P-line to GND, and 1k-ohm pull-up on the N-line to 3.3V) to force a stable Logic LOW state when the driver is High-Z?
Logic LOW vs Logic HIGH: If external biasing is necessary, does it strictly need to be biased to Logic LOW for proper JESD204B SYSREF operation (to prepare for a clean rising edge), or would biasing it to Logic HIGH also be acceptable?
I would appreciate your detailed technical explanation. Thank you!
