Hi Dan,

We are investigating your inquiry, I'll get back to you by the end of the week. 

Best,

Jaryd

Hi Jaryd,

Thanks for your reply.

I will be using ECS-TXO-20CSMV4-250-AN-TR for the clock source.

Rgds

Dan.

Hi Dan,

Since you're using a single-ended clock input, it would be best to set the register to LVCMOS buffer enabled. This would be done by setting R24[15] (IP_PRIREF_BUF_SEL) to 0h. The single-ended swing capabilities depend on the value of VDD_REF you're using, so ensure that this value is appropriate for your 800mVpp single-ended swing.

Is there a reason you would need differential buffering enabled for your application?

Best,
Jaryd

Hi Jaryd,

Is the below input interface condition work fine for CDCE6214 in single-ended input? I bias the input to 0.5VDD_REF to ensure the clipped sinewave superimpose on the middle of the input range.  Do you foresee any issue with input slew rate requirement (1V/ns) with this connection?

Rgds

Dan

Hi Dan,

The re-biasing portion of your interface looks fine. The only issue I see is with how you're setting PRIREF_N, as this should be set to the DC bias point (0.5VDD_REF) and not GND. This can be accomplished with another resistive voltage divider network, similar to what you have in your schematic.

Also you may need to increase the swing of your input. Below are the input low and high voltages that are required for the device to register "high" and "low" voltages. For a VDD_REF input of 1.8V, this means VIL = 0.36V and VIH = 1.44V. In this application with a common mode of 0.9V and a swing of 800mVpp, the signal swings down to 0.5V (above VIL) and up to 1.3V (below VIH).

I don't see any issues with the slew rate requirement using this re-biasing configuration.

Best,
Jaryd

Hi Jaryd,

I saw another thread with similar question. The TI design team commented that for a clipped sinewave, CDCE6214 can use differential input mode and we just need to use ac coupling for the input because it has internal bias in differential mode. Also, 0.8Vpp is within the acceptable input range for differential mode. This configuration use less component count. It is same as my first first. Can you help to confirm it is okay?

25MHz --------||----------PRIREF_P (pin5)

GND-----------||-----------PRIREF_N (pin6)

Below is the threat topic I saw.

CDCE6214-Q1: Using 0.8Vpp VCTCXOs as a reference input

Hi Dan,

Apologies for the confusion, it looks like the design team did approve this method for a single-ended input to PRIREF. Also the 0.8Vpp does meet the acceptable input range spec for differential mode.

So yes, the configuration looks good for your application.

Best,
Jaryd