AM62A7-Q1: CAN clock source

Hi,teams

We have checked that the reference clock for the software configuration CAN is MCU_HFOSC0, which is an internal high-frequency oscillator connected to the external main crystal oscillator. Could you please explain how the internal clock tree is set up and what the precision of the multiplication of MCU_HFOSC0 is?

Thanks,

Xiwen

Hello,

This thread will be assigned to the subject matter expert. Please allow some time for a response.

Hello Liu Xiwen,

Here is the TI Sysconfig / Clock tree tool diagram corresponding to the MCAN0 functional clock PLL path:

Refer the Figure, MAIN Domain PLLs Integration of the Section, MAIN Domain PLLs Overview of the AM62x TRM.

The MCU_HFOSC0_CLKOUT=25 MHz can be mapped to the MAIN_PLL0.MAIN_PLL0_REF_CLK input. The MAIN_PLL0 multiplies the SYS_CLK 25 MHz input frequency by 80 and outputs  2.0 GHz to the high frequency PLL0 divider matrix. 

For the MCANs power/clock specific information, refer the Section, Modular Controller Area Network (MCAN) / Subsection, MCAN Integration of the AM62Ax TRM

The register MAIN_CTRL_MMR_CFG0_MCAN0_CLKSEL[1:0] MCAN0_CLKSEL_CLK_SEL  default value = 0 selects the MAIN_PLL0 high frequency dividers  as source of the MCAN0 FCLK. The MAIN_PLL0_HSDIV4_CLKOUT divider can be programmed in the the range 1 - 128 from the bitfield MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL0[6:0]HSDIV but since this clock is shared with other modules - DCC0 and MCU_DCC0, changing its value to different than default will impact also the DCC0 and MCU_DCC0. The default HSDIV=24 (real divider value = HSDIV+1=25) value defines the MCAN0_FCLK to be 2000 MHz /25 = 80 MHz.

A source different than the high frequency divider can be selected changing the  value of the bitfield MCAN0_CLKSEL_CLK_SEL. For instance 0x3 selects directly the HFOSC0_CLKOUT=25 MHz to be the MCAN0_FCLK source clock, bypassing the main PLL0.

I hope this helps !

Let me know if you have further questions ?

Best Regards

Anastas Yordanov

Hi,Anastas Yordanov 

Thank you for your reply.

Anastas Yordanov said:

The default HSDIV=24 (real divider value = HSDIV+1=25) value defines the MCAN0_FCLK to be 2000 MHz /25 = 80 MHz.

Can I understand it this way: MCU_HFOSC0 is my external input clock at a frequency of 25 MHz. The default configuration of the MCAN in AM62A7 uses the 80 MHz clock obtained by dividing the 2G MAIN_PLL0 clock (80*MCU_HFOSC0) ?

The following picture shows the configuration interface of the software colleague MCAN. Looking at the clock of MCAN, it is 25 MHz. Could you please help confirm this?

Additionally, we are using CANFD with a data rate of 2Mbps. A high-precision clock is required. I would like to know if the precision of the PLL used by MCAN is sufficient for our application of CANFD.

Thanks，

Xiwen

Hello Liu,

Thank you for sharing more details !

Are you sure the Input clock Frequency = 25 MHz defined in your MCAN Sysconfig panel is applicable to the MCAN0 instance functional clock. I  see MCU_TIMER0. I will also check the setting and confirm.

Apart from this, a direct supply of HFOSC0 frequency to MCAN is possible:

Anastas Yordanov said:

A source different than the high frequency divider can be selected changing the  value of the bitfield MCAN0_CLKSEL_CLK_SEL. For instance 0x3 selects directly the HFOSC0_CLKOUT=25 MHz to be the MCAN0_FCLK source clock, bypassing the main PLL0.

Speaking generally, I think the fractional MAIN_PLL0 shall have a negligible impact on the preciseness of the MCAN clock. The preciseness will depend foremostly on the preciseness of the external crystal oscillator that you use. 

But I will try to crosscheck and  follow-up with the needed information today.

Thanks

Best Regards,

Anastas Yordanov

Hi,Anastas

I'm not sure if the clock of MCAN is 25 MHz. The image shows the clock configuration as seen by our software colleagues for AM62A74, which is 25 MHz. So I would like to confirm this with you.

Thanks,

Xiwen

Hi Liu,

Does the customer engineer also have the exported Clock Tree tool configuration of the MCU_MCAN1 (this is the clock tree screenshot I already provided) - this is what is relevant regarding the MCAN_FCLK frequency and power clock management.

The Sysconfig clock tree tool exported configuration looks like:

As I tried to configure the MCU_MCAN1 device in Sysconfig, as follows:

By default (similar to MCAN0) the MCU_MCAN1_FCLK is 80 MHz. By default after PoR it is also gated in the WKUP Power Sleep Controller 0 (not running) and requires the software to enable it. This is reflected in Sysconfig generated software via  the Clock Tree modifiable LPSC (LPSC_MCU_MCANSS_1 local power sleep controller) setting.

liu xiwen said:

I'm not sure if the clock of MCAN is 25 MHz. The image shows the clock configuration as seen by our software colleagues for AM62A74, which is 25 MHz. So I would like to confirm this with you.

A: The clock frequency (25 MHz) shown on your screenshot is NOT the MCU_MCAN1 input functional clock, rather this is the MCU domain System timer frequency. 

Regarding the relation between the MCU MCAN1_FCLK and the desired CAN Nominal and Data bit rates you may find the below link very useful:

How to calculate the MCAN nominal and data bit rates

You may check also these E2E resources:

(+) AM620-Q1: MCAN Bit rate (bits per second) & Sampling Point Formula Or How to Calculate CAN Baud Rate? - Processors forum - Processors - TI E2E support forums

https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/10_01_00_32/exports/docs/api_guide_am64x/DRIVERS_MCAN_LLD_PAGE.html

Allow me some time to discuss the MCAN CLK / bit rate preciseness issue ?

Best Regards

Anastas Yordanov