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CDCE6214: PLL not indicating Locked Status

Gian-Luca Brazerol
Prodigy 20 points

Part Number: CDCE6214

Dear TI Team,

We are using the CDCE6214 to generate the reference clock for multiple SERDES blocks within multiple FPGAs. The setup is that one of the FPGAs configures the PLL via I2C, as the device is in Fallback-Mode. After configuration, all the desired output frequencies are present at the outputs. However, I encountered an issue where the PLL-Locked Status Bit is not asserted (R7[0]), even though the LOCKED output pin is high.

The reason I came across this issue was because I encountered DPA issues within the SERDES blocks, and the standard deviation of the output frequency was large (250kHz for 100MHz), which could be the source of the DPA-Locking Issue.

Is there a setup where the Locked Status Bit is '0', even though the Locked Pin is high, and what does it mean? Is the PLL not configured correctly? I appended a list of all the configurations I made using the CDCE6214-Q1 Registers User Guide and a schematic snipped. R1201, R1206, R1210, R1213 and R1215 are not fitted.

pll_schematic.png

For the register configuration, I only modified the bitfields that I thought were necessary according to User Guide. The remaining bits were untouched.

pll_config.txt 

I also tried to disable the Digital Lock Detect (R81[3]: 0x1) and to widen the Locked Detect Window (R50[10:8]: 0x7), but did not succeed. 

Thank you for help,

Gian-Luca

 

  • 0
    TI__Prodigy 650 points

    Hi Gian,

    Our sincere apologies for the delayed response on this. While I look at your configuration and try to debug, what would really help speed this up is if you can share the TICS pro exported hex file or the save device configuration. Was TICS Pro not used to setup the device? To avoid common pitfalls, we usually recommend that you first load full default EEPROM config first using TICS Pro (EVM default), verify PLL locks with the TI default config, then apply your custom register writes on top. Also, are you verying that the lock signal as a waveform on the scope to see if it's a continuous lock signal or toggling?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Jain
    Prodigy 20 points

    Hi Rishabh,

    I configured the device with the TICS pro as instructed, and exported the .hex file. Unfortunately, we did not use this software to setup the device and verify its operation, as we do not have an Eval Kit at the moment.

    Regards,

    Gian-Luca

    Fullscreen 6403.HexRegisterValues.txt Download 
    R85	0x00550000
R84	0x00540000
R83	0x00530000
R82	0x00520000
R81	0x00510004
R80	0x00500000
R79	0x004F0208
R78	0x004E1000
R77	0x004D0000
R76	0x004C0188
R75	0x004B4008
R74	0x004AA181
R73	0x00491000
R72	0x00480005
R71	0x00470006
R70	0x00460808
R69	0x0045A181
R68	0x00441000
R67	0x00434005
R66	0x00420006
R65	0x00410808
R64	0x0040A181
R63	0x003F1000
R62	0x003E0005
R61	0x003D0000
R60	0x003C6008
R59	0x003B8008
R58	0x003A502C
R57	0x00391000
R56	0x00380005
R55	0x0037001E
R54	0x00363400
R53	0x00350069
R52	0x00345000
R51	0x003340C0
R50	0x003207C0
R49	0x00310013
R48	0x00301A14
R47	0x002F0A08
R46	0x002E0000
R45	0x002D4F80
R44	0x002C0318
R43	0x002B0051
R42	0x002A0002
R41	0x00290000
R40	0x00280000
R39	0x00270000
R38	0x00260000
R37	0x00250000
R36	0x00240000
R35	0x00230000
R34	0x00220000
R33	0x00212710
R32	0x00200000
R31	0x001F0000
R30	0x001E0032
R29	0x001D0000
R28	0x001C0000
R27	0x001B0005
R26	0x001A0000
R25	0x00190400
R24	0x00180718
R23	0x00170000
R22	0x00160000
R21	0x00150000
R20	0x00140000
R19	0x00130000
R18	0x00120000
R17	0x001126C4
R16	0x0010921F
R15	0x000FA037
R14	0x000E0000
R13	0x000D0000
R12	0x000C0000
R11	0x000B0000
R10	0x000A0000
R9	0x00090000
R8	0x00080000
R7	0x00070000
R6	0x00060000
R5	0x00050008
R4	0x00040000
R3	0x00030000
R2	0x00020003
R1	0x00012310
R0	0x00001004

  • 0 in reply to Gian-Luca Brazerol
    TI__Prodigy 650 points

    Hi Gian,

    You should still be able to use your normal setup to write this data. The first 2 bytes are address followed by data. For example R72 0x00480005 essentially means you should write 0x0005 to Address 0x0048. Please make sure you write these in reverse order, start from R85 down to R0. This thread should help you - CDCE6214: Programming CDCE6214 from MCP2221A over I2C - Clock & timing forum - Clock & timing - TI E2E support forums

    Regards,

    Rishabh

  • 0 in reply to Rishabh Jain
    Prodigy 20 points

    Hi Rishabh,

    I configured the device accordingly. While I do get the desired output frequencies as before, the LOCK_DET bit remains low, just as before, even with the Soft-Reset bit triggered after configuration. We will comission a second HW and see wether the devices behaves the same.

  • +1 in reply to Gian-Luca Brazerol
    TI__Prodigy 650 points

    Hi Gian,

    While nothing seems wrong with the configuration at the first glance, there is a very nuanced mistake in the PLL section when compared to the datasheet. Please refer section "7.3.2.1 PLL Configuration and Divider Settings" I have given a snapshot below

    Fullscreen HexRegisterValues_CDCE6214.txt Download 
    R85	0x00550000
R84	0x00540000
R83	0x00530000
R82	0x00520000
R81	0x00510004
R80	0x00500000
R79	0x004F0208
R78	0x004E1000
R77	0x004D0000
R76	0x004C0188
R75	0x004B4008
R74	0x004AA181
R73	0x00491000
R72	0x00480005
R71	0x00470006
R70	0x00460808
R69	0x0045A181
R68	0x00441000
R67	0x00434005
R66	0x00420006
R65	0x00410808
R64	0x0040A181
R63	0x003F1000
R62	0x003E0005
R61	0x003D0000
R60	0x003C6008
R59	0x003B8008
R58	0x003A502C
R57	0x00391000
R56	0x00380005
R55	0x0037001E
R54	0x00363400
R53	0x00350069
R52	0x00345000
R51	0x003340C0
R50	0x003207C0
R49	0x00310013
R48	0x00301A14
R47	0x002F0A08
R46	0x002E0000
R45	0x002D4F80
R44	0x002C0318
R43	0x002B0051
R42	0x002A0002
R41	0x00290000
R40	0x00280000
R39	0x00270000
R38	0x00260000
R37	0x00250000
R36	0x00240000
R35	0x00230000
R34	0x00220000
R33	0x00212710
R32	0x00200000
R31	0x001F0000
R30	0x001E0032
R29	0x001D0000
R28	0x001C0000
R27	0x001B0004
R26	0x001A0000
R25	0x00190400
R24	0x00180718
R23	0x00170000
R22	0x00160000
R21	0x00150000
R20	0x00140000
R19	0x00130000
R18	0x00120000
R17	0x001126C4
R16	0x0010921F
R15	0x000FA037
R14	0x000E0000
R13	0x000D0000
R12	0x000C0000
R11	0x000B0000
R10	0x000A0000
R9	0x00090000
R8	0x00080000
R7	0x00070000
R6	0x00060000
R5	0x00050008
R4	0x00040000
R3	0x00030000
R2	0x00020003
R1	0x00012310
R0	0x00001004

    In the config shared, the PLL is set to Frac Mode 1 but single PFD mode is enabled, and I suspect this to be the issue causing recurrent lock/unlock. Moreover, since your outputs are integer multiples of the input, to extract the best performance please set it to integer mode and then you can use the single PFD mode. I have made these changes in the attached config. Please check and let me know, we will then plan out the next course of action accordingly.

    Regards,

    Rishabh

  • 0 in reply to Rishabh Jain
    Prodigy 20 points

    Hi Rishabh,

    I think that was it, I now get the PLL-Locked status from the register reading. Thank you very much for your support.

    Regards,

    Gian-Luca

  • 0 in reply to Gian-Luca Brazerol
    TI__Prodigy 650 points

    Glad I could help Gian.

    Regards,

    Rishabh