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CDCM7005 Frequency planning and jitter estimation

kiruba sankar
Prodigy 190 points
Other Parts Discussed in Thread: CDCM7005, CDCM61001, CDC3RL02, CDCE62005, CDCS503

Hi,

We are planning to use CDCM7005 in our design.

Design requirements:

#################

1. 5 Clock outputs (Fout = 102.4MHz) to drive 4 ADCs and External reference.

2. We are planning to use ADC AD9467 (Analog devices).  The ADC supports 75dBc SNR (Input 70+/- 10MHz  / 1.5MHz to 30MHz , Sampled at 102.4MHz) . 

3. CDCM7005 should lock to an External OCXO (Reference Clock) with sine wave 10MHz  (Phase noise -130dBc/Hz @10KHz and higher) which is yet to be selected.

Query:

#####

1. Will the CDCM7005 will provide sufficient low jitter clock to meet the SNR spec of the ADC (RMS clcok jitter should be less than approximately 350fS.  Correct me if I am wrong).

2. Since the OCXO is yet to be selected.  How to derive the jitter requirement of the OCXO from the design requirement for the CDCM7005 (RMS Jitter < 350fS)

3. Is there any frequency planner available for CDCM7005 (Such as one available for CDCM61001  http://e2e.ti.com/support/clocks/m/videos__files/576535.aspx  ).  I want to derive the VCXO frequency for the 10MHz reference and 102.4MHz output with the possible M, N & P divider values.

4. We are planning to use the VCXO (http://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf).   Please let me know how can I estimate the phase noise  of CDCM7005 output from VCXO and OCXO phase noise information.  I refereed the http://e2e.ti.com/support/clocks/f/48/t/153019.aspx.  But unable to find out where to give the phase noise informations of the VCXO and OCXO to get the resultant phase noise of the CDCM7005.

Regards,

Kiruba

 

 

 

 

 

  • 0
    TI__Expert 3985 points

    Hi Kiruba,

    thank you for your interest in our device. Please find below the answer to your questions:

    1) the jitter requirement for the ADC depends on the maximum analog input frequency which is sampled, the target SNR and the aperture jitter of the ADC itself. For example if you want to sample a 50MHz input signal with an SNR of 78dB with the AD9467 (60 ps typ aperture jitter) your clock jitter does not have to exceed 390fs rms. If you consider some margin due to the noise of the analog signal (which also degrades the overall SNR), 350fs should be your targeted rms jitter.
    At this point, I would give you another advice about the reference source. A sinewave clock signal is more sensitive to noise than a square wave one. If you like to stick with a sinewave clock source, you should have at least a high slew-rate signal. Otherwise a clipped sine wave or square wave source is even a more clean source.

    2) the CDCM7005 will work as jitter cleaner which behaves like a very lowpass filter. Therefore you should take care of the input reference performance in the frequency range up to the device PLL- bandwidth which you defined. For example if you set the External Loop Filter in such a way that the PLL bandwidth is 100Hz, you should take care of the phase noise of the input reference up to a offset frequency of 100Hz. From that point on, the output clock perfromance will be dominated by the external VCXO you are going to use.

    3) In the following screen shot, you can find the divider value you need to set into the device

    4) Here some other link you may use for your project. They include same calculator to see the noise contribution from each PLL block and the GUI interface to program the device.

    http://www.ti.com/tool/cdc-cdcm7005-calc

    http://www.ti.com/product/cdcm7005

    I hope this fulfill your requests.

    Best regards,

    Leandro

  • 0 in reply to Leandro_z
    Prodigy 190 points

    Hi Leandro,

    Thanks for your detailed clarifications on query 1 & 2.  Please clarify me further on the 3 & 4

    >> 3) In the following screen shot, you can find the divider value you need to set into the device

    I tried that "Texas Instruments CDCM7005 SPI Software".  How the divider values for the M divider =100, N divider =768, P-divider=16 were acheived by the software (Where we have give the Ref_Clk frequency and the desired Output_Clock as input in the software to calculate the divider values.  How do I find the required VCXO frequency for 102.4MHz output clock)

    >> 4) Here some other link you may use for your project. They include same calculator to see the noise contribution from each PLL block and the GUI interface to program the >>>device.

    >> http://www.ti.com/tool/cdc-cdcm7005-calc

    >> http://www.ti.com/product/cdcm7005

    I tried the excel version of the tool and I am unable to find where should I include the phase noise information of the VCXO and OCXO (Ref_Clk) to estimate the output phase noise of the CDCM7005.  Please clarify.

    Regards,

    Kiruba

  • 0 in reply to kiruba sankar
    TI__Expert 3985 points

    Hi Kiruba,

    the current available version of the GUI does not include a frequency planner tool. The VCXO possibilities for a defined output frequency (i.e. fout=102.4MHz) are given by multiplying fout x1, x2, x3, x4, x6, x8, x16. In your case I wanted to suggest you a VCXO frequency of 614.4MHz (which is 102.4M x 6).

    The next step would be to calculate the M, P and N values. How to do this? You should define the PFD frequency, which is given by the greatest common divisor between the selected VCXO frequency and the input reference frequency (i.e. 10MHz), which you can get within the available M, P and N value range. In your case the greatest common divisor is 100kHz. In case you have multiple choices I would suggest you to pick up always the highest possible PFD frequency.  

    Based on the calculated PFD frequency, you can derive the values of M, P and N dividers.

    With regards to TI PLL sim, the excel version provides you only an high-level approach to the device, while the Labview version has more features, like the possibilty to perform the noise contribution analysis. As you can see in the attachement, under "Noise Cons." menu you can insert the Inpur reference phase noise levels, the VCXO phase noise and you get an estimation of the output phase noise. In the Filter & PLL Cal. section, you can also tried out different Loop Filters in order to achieve the best performance out of the CDCM7005.

    Let me please ask you for which application you want to use this device.

    Feel free to ask for further support if needed.

    Regards,

    Leandro

     

  • 0 in reply to Leandro_z
    Prodigy 190 points

    8764.QUAD ADC GENERAL BLOCK - TI Support.pdf

    Hi Leandro,

    Once again thanks for your detailed clarifications.  Currently I dont have access to Labview I am checking for the possibilities to use  the labview version of the tool.   

    Regarding the application we are planning to use the CDCM7005 to clock the Four ADCs.  This is a XMC based quad channel ADC card.  It may be used for Software defined radio.  Here with I have attached the block diagram for your reference.  

    There should be an option to clock the on board ADC either by internal or external clock source.  So the board has 3 clocking option
     
    Option1: ADC clock is directly driven by the EXTERNAL CLK IN
    ####################################################
    During this mode of operation the required ADC clock will be directly driven from external source (81.4MHz or 102.4MHz).  The switch position is as follows
     
    Single SPDT Switch position - RFC connects to RF2
    Dual SPDT Switch position - RFC1 connects to RFC2
     
    The Amplifier and power divider will be used to split the clock to the four ADCs. 
     
     
    Option2: On board ADC clock is sync to the EXTERNAL CLK IN
    ######################################################
     
     
    During this mode of operation the required ADC clock will be generated by CDCM7005 (81.4MHz or 102.4MHz) and its output will be sync to the external clock input (10MHz) directly driven from external source.  The switch position is as follows
     
    Single SPDT Switch position - RFC connects to RF1
    Dual SPDT Switch position - RFC2 connects to RF2 (RFC1 is position is dont care)
     
    The Amplifier and power divider will be used to split the clock to the four ADCs. 
     
    Option3: On board ADC clock will be driven to EXTERNAL CLK IN
    #######################################################
     
    During this mode of operation the required ADC clock will be generated by CDCM7005 (81.4MHz or 102.4MHz) and a copy of this clock will be given as output to the "external clock".  The switch position is as follows
     
    Single SPDT Switch position - RFC connects to RF2
    Dual SPDT Switch position - RFC2 connects to RF2 & RFC1 connects to RF1
     
    The Amplifier and power divider will be used to split the clock to the four ADCs. 

    Since our OCXO (Ref_clock = 10MHz) is a sine wave, we are planning to use a sine to square wave converter (since CDCM7005 doesnt support sine wave input).    Please refer http://e2e.ti.com/support/clocks/f/48/t/163080.aspx where I was recommended to use ILMV7219 for sine wave to square wave conversion.   I was just wondering device like "CDC3RL02" might have been better suit my application however it just supports 1.8V but CDCM7005 needs 3.3V.    Please let me know your suggestion if any to implement the clocking solution for the ADC.

    Regards,

    Kiruba

  • 0 in reply to kiruba sankar
    TI__Expert 3985 points

    Hi Kiruba,

    sorry for the delayed answer. The CDC3RL02 could work as Sine-to-Square Wave buffer. Do you have the chance to place a 3.3V supply in your board as well?

    I was also wondering about the clock solution you are considering in for your FPGAs (Virtex 5 and Virtex 6). The CDCE62005 could be used for those FPGAs.

    Thanks and best regards,

    Leandro

  • 0 in reply to Leandro_z
    Prodigy 190 points

    Hi Leandro,

    I mean to say that since CDC3RL02 supports only 1.8V output I am unable to use it with CDCM7005 (Since the CDCM7005 requires 3.3V compatible LVCMOS).  Any recommendation for the interface between these two chips highly appreciated.  Yes, we have on board 3.3V.  And as you said we are planning to clock the FPGA with the CDCM7005.

    Regards,

    Kiruba

     

  • 0 in reply to Leandro_z
    Prodigy 190 points

    Hi Leandro,

    I mean to say that since CDC3RL02 supports only 1.8V output so I am unable to use it with CDCM7005 (Since the CDCM7005 requires 3.3V compatible LVCMOS).  Any recommendation for the interface between these two chips highly appreciated.  Yes, we have on board 3.3V.  And as you said we are planning to clock the FPGA with the CDCM7005.

    Regards,

    Kiruba

     

  • 0 in reply to kiruba sankar
    TI__Expert 3985 points

    Hi Kiruba,

    sorry for the late response. I would suggest you to use the CDCS503. This device has a wide input hysteresis that can make it work also with small slew rate input signal.

    Regards,

    Leandro

     

  • 0 in reply to Leandro_z
    Prodigy 190 points

    Hi Leandro,

    I am afraid are you recommending the CDCS503 as an interface between the CDC3RL02 (1.8V LVCMOS output) & CDCM7005 (3.3V LVCMOS input)?  Since CDCS503 is operating at 3.3V and its VIH min is 0.7VCC (2.31V).  Please clarify.

    Regards,

    Kiruba

  • 0 in reply to kiruba sankar
    TI__Expert 3985 points

    Hi Kiruba,

    I meant to use the CDCS503 instead of CDC3RL02. But in this case you should better use a Reference Input of 30MHz and set the M divider in the CDCM7005 to 300. Would this be possible for you?

    Regards,

    Leandro

  • 0 in reply to Leandro_z
    Prodigy 190 points

    Hi Leandro,

    My reference clock is 10MHz sine wave.  Mean while I found a chip that support sine wave input and LVCMOS output.

    PL130-07SI  (Sine to square wave converter) from phase link

    Thanks a lot for your efforts and clarifications to resolve my queries.

    Regards,

    Kiruba

  • 0 in reply to kiruba sankar
    Prodigy 40 points

    Hi,
       We are using the Jitter cleaner CDCM7005 in our board.We are providing VCXO Ref.input from Si571AEC000107DG
     & reference clock from external OCXO 501669013 Wenzel associates part 501-09451. We are facing issue in CDCM7005 locking.
    We want to know whether the VCXO & reference signal are synchronous in their rising edge.
    What will happen if the VCXO & reference input are 180 degree out of phase.
    We have got the PDF as 400KHz & kept lock detect window to 18.5ns.
    We want to know how the rising edge synchronous lock is ensured using our set up,& how to achieve locking?

     

    Thanks & Regards,

    S.Sathiya Seelan.