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LMK04033 PLL - Phase Relationship

Adam Hoover
Expert 5275 points
Other Parts Discussed in Thread: LMK04033, LMK04906, LMK03200

Hi team,

Please help support the following customer request:

I'll provide some background to help understand the problem before getting to my question:

So, as I mentioned, we are working with the LMK04033 PLL.  We are feeding it a low jitter 10MHz clock into its PLL2 input (PLL1 section is disabled) and are synthesizing a 104.88MHz clock at one of the PLL outputs.  The 104.88MHz clock is being used to Equivalent-Time Sample a recurring signal 100ns (10MHz) in duration. The phase relationship between the two clocks will be unique for 12.5us (1311 cycles of 104.88MHz and 125 cycles of 10MHz) at which point a 1311 sample reconstruction of the signal will be complete and the process will start again.  The two clocks are fed into an FPGA which is being used to deinterleave the samples as they are received.  The reordering of samples can be performed with just the 104.88MHz clock and by understanding the known relationship between the 2 frequencies (add 125 modulo 1311).  This leaves us with a 1311 samples that are in order (only relative to each other) in a circular buffer, but with no absolute signal start or end point. 

Our problem is that we would like to be able to determine the absolute position of the samples within the window and do so consistently even if our electronics are power cycled.  To be able to do this, we need to know not just that the two frequencies are phase-locked, but also be able to understand the relationship between their phases.  For example, at only one point during any given 12.5us period, the rising edges for both clocks will occur simultaneously (or close to it) - Let's use that as absolute reference point and assign it to be position 1 of 1311 within the window.

Is there any way to use the PLL (and/or perhaps an FPGA) to accomplish this goal?

Something I have already tried doing was to force synchronize the two clocks together by sending the SYNC* pin of the PLL a reset pulse which I synchronized to the 10MHz clock.  Unfortunately there was unacceptable amount of jitter between the rising edge of the SYNC* line and the 104.88MHz output.

I have the PLL configuration file as per the National Clock Design tool, and can send this internally if it will help.

Thanks,

Adam Hoover

  • 0
    TI__Mastermind 32575 points

    To achieve deterministic phase relationship between the input clock and output clocks, you need a PLL that supports zero-delay (0-delay) feedback mode. LMK04033 does not support 0-delay. A few low-jitter PLLs with zero delay mode include LMK04800 family / LMK04906 dual PLL jitter-cleaner/clock gen family and LMK03200; these devices support internal or external loopback.

    Refer to section 7.9.3 in the LMK04800 Datasheet for usage of 0-delay mode. The SYNC functionality and digital delay support phase sync/alignment and supplement the 0-delay mode operation. 

    Regards,

    Alan