• State
  • Locked Locked
  • Replies 12 replies
  • Subscribers 22 subscribers
  • Views 1930 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CLOCK GENERATOR

eli
Guru 13485 points
Other Parts Discussed in Thread: CDCM6208

Looking for a clock generator to support below needed clocks:

1x LVDS -  125MHz for QSGMII (low phase noise < 1ps),

1x LVDS -  125Mhz for Marvell PHY.

1x LVDS - 156.25MHz for 10GBASE-T (Xilinx Serdes)

3x LVDS - 200Mhz  (DDR Clock & system Clock for FPGA)

The 125Mhz and 156.25MHz jitter mask is attached below:

  • 0
    TI__Guru** 108760 points

    Hi Eli,

    you can try CDCM6208, it could generate all your necessary clocks with a 25MHz crystal. See attached configuration.

  • 0 in reply to Noel Fung
    Guru 13485 points

    Hi Noel

    Thanks!!

    Can you send me the link for the goui?

  • 0 in reply to eli
    TI__Guru** 108760 points

    here you are: http://www.ti.com/lit/zip/scac134

    Pls also visit the cdcm6208 webpage for more application information.

  • 0 in reply to Noel Fung
    Guru 13485 points

    1)Dose the outputs meet the requested jitters?

    2)PHY: 125MHz as follow:

  • 0 in reply to eli
    TI__Guru** 108760 points

    Hi Eli,

    Yes, we are able to meet this jitter requirement with lots of margin. From datasheet page 19, Figure 2, you can see the jitter for 156.25MHz output is just 263.7fs rms. The jitter will be similar if the output is 125MHz.

  • 0 in reply to Noel Fung
    Guru 13485 points

    Hi,

    It look good for 156.25MHz.

    At 100k offset it is about -132dBc/Hz for 156.25. For 125Mhz this figure will be higher, and might be above required -131dBc/Hz.

     Could you get a plot for 125Mhz?

  • 0 in reply to eli
    Guru 13485 points

    Hi,

    See below and advise:

    This is the plot I got. I rather use the integer divider for lowest Jitter.

    I need help with the Loop Filter. I used following values (be below) and got Phase noise figure Marginal for 125MHz at 10K offset.

    Ignore the 200Mhz, I need the 200MHz for DDR prior to CDCM6208 configuration.  (couldn't find this frequency at pre-configuration options).

     

  • 0 in reply to eli
    TI__Guru** 108760 points

    Hi Eli,

    Suggest use higher charge pump current and wider loop bandwidth. For example, use 2.5mA CP current and set the loop bandwidth to 400kHz. Phase margin equals 70deg is fine.

    Below is a plot also with 25MHz crystal input, 125MHz output that we took a couple of years ago. At 10kHz offset, the phase noise is close to -135dBc/Hz.

  • 0 in reply to Noel Fung
    Guru 13485 points

    Thanks again!!!

    Do you have recomendation regarding oscillators for these frequencies?

    Eli

  • 0 in reply to eli
    TI__Guru** 108760 points

    Hi Eli,

    25MHz crystal is a very common part, I believe crystals from any vendor can work as long as the crystal electrical specification as shown in the datasheet is met.

  • 0 in reply to Noel Fung
    Guru 13485 points

    In CDCM6208 design, I don't need the PRI_REF input (I use crystal). 

    How should I connect the PRI_REFP/ PRI_REFN Pins?

    Should I tie PRI_REFP via pull-up to VDD and PRI_REFN to GND via pull-down?

  • 0 in reply to eli
    TI__Genius 10320 points

    Hi Eli,

    If these buffers are not being used, we recommend disabling the input and pulling one side to Vdd with a 1k resistor and the other side to GND with a 1k resistor.

    Gabe