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lmk04033 shematic issues

Edward_edward
Prodigy 165 points

Hello everyone I have few question about the lmk04033b. I will use 20 MHZ cyrstal osc for OSCin ports.  Should I use another crystal oscillator for CLKin0 and CLKin1 ports and if I excite these two port with same oscillator which is factor of 20 MHZ crystal osc. is this ok for the lmk04033b.   in evaluation board schematic there are two Loop filter design for PLL2 Loop filter if I use crystal osc. should I remove VCXO loop filter circuit in my design. 

Thanks in advance

  • 0
    TI__Mastermind 32575 points

    Assuming you're using a clean 20 MHz XO, you may drive OSCIN port as a reference clock for PLL2 to generate the clock outputs from the VCO.  You do not need to use PLL1 as a jitter cleaning stage if your 20 MHz XO is already clean enough.

    When PLL1 is not used, you can leave CLKIN0/0*, CLKIN1/1*, and CPout1 pins floating.  Also, in register programming, make sure to tri-state PLL1 charge pump (R13[bit 14] = 1) and clear the PLL1 DLD Run Control bit (R10[bit 29] = 0) to allow PLL2 VCO calibration to run without any dependency on PLL1's lock state.

    Regards,
    Alan

  • 0 in reply to Alan O
    Prodigy 165 points

    Alan thanks for quick reply    According to clock design tool, VCXO is 20 MHz and I am thinking to use fox xpresso FVXO-LC53 SERIES vcxo which is low jitter in datasheet. you sad I can leave floating CLKIN0/0*, CLKIN1/1* and CPout  also LOS0 and LOS1.  What if I use those ports..... in this option should I choose another xo which is equal value of 20 MHz VCXO or factor of 20 MHz VCXO. And  is it possible to apply 20 MHz VXCO to CLKIN0/0*, CLKIN1/1*  ports and leave OSCIN port floating.