LMK04033 Clocking

Hi Edward,

This application is valid, but note that OSCin has some minimum slew rate limitations that some sinewave VCXOs may not meet. Additionally, better perfomance is yielded as PLL2  phase detector frequency is increased therefore allowing for wider loop BW for PLL2.

Gabe

Hi Gabe

thanks for quick reply.... According to your expression should I increase VCXO frequency in Clock design tool I only increase PLL2 PDF with increasing of VCXO and I didnt find slew rate for VCXO which I use for OSCin port and there is some values which is related with slew rate I think

Output Symmetry (See Drawing Below)----> @ 50% VP-P Level(normal) ------>45% ~ 55% (max)
Output Enable (PIN # 2) Voltage ---->VIH ----> 70% VDD(max) 
Output Disable (PIN # 2) Voltage-----> VIL-----> < 30% VDD (max)
Cycle Rise Time (See Drawing Below)----> TR----> 20%~80%-------> 400 pS (max)
Cycle Fall Time (See Drawing Below) --->TF---> 80%~20%-----> 400 pS (max)

does this vcxo meet with min slew rate limitation of OScin port 

Regards

Edward

Hi Edward,

This is dependent on the VCXO's Vpp. The LMK04000 family has a spec of minimum slew rate of 0.15 V/ns between 20% and 80%. What is the VCXO swing ?

Gabe

Hi Gabe

vpp and other parameters related with Vpp in this picture below

thank you very much fro your helping 

regards

Edward