• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 21 subscribers
  • Views 1535 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: Determinstic timing using SYNC

Steven Naboicheck
Prodigy 20 points
Other Parts Discussed in Thread: LMK04033, LMK04826, LMK04821

Hello,

We are in the process of redesigning a couple of our boards and presently use the LMK04033. The problem we are running into is the synchronization function that allows the aligning of the output clock edges is not deterministic for this device and thus prevents us from reliably synchronizing multiple boards to within one clock period of the clock distribution path in a repeatable manner. This is due to the slow internal slew rate of the SYNC that is being sampled at a .  We are hoping that the LMK04826 overcomes this issue.  Our goal is to be able to consistently sample the SYNC signal using the distribution clock edge in a deterministic manner.  Questions follow:

1.  If the SYNC input pin doesn't suffer the slow internal slew rate issue than can you provide the setup and hold time required for this signal so we can guarantee we get a deterministic result?

2. Does using CLKin0 as the SYNC input avoid the slow slew rate issue and if so what are the setup and hold times for this mode? 

3. Can we use SYSREF in a deterministic manner to align the clock outputs?

4. What is the sampling rate of the SYNC signal for the LMK04828B and do you have a better timing diagram for this process?

Thanks!

  • 0
    TI__Mastermind 28560 points

    Hello,

    Yes the LMK04826 does have some improved abilities to deal with what you are speaking of.

    Steven Naboicheck said:
    1.  If the SYNC input pin doesn't suffer the slow internal slew rate issue than can you provide the setup and hold time required for this signal so we can guarantee we get a deterministic result?

    I'm afraid I don't have the setup and hold times for this type of application of the pin.

    Steven Naboicheck said:
    2. Does using CLKin0 as the SYNC input avoid the slow slew rate issue and if so what are the setup and hold times for this mode?


    Again, at this time I don't have specs for this, but you are correct about the CLKin0 path being a good option for avoiding CMOS circuit paths for improved performance.  CLKin0 is better.

    Steven Naboicheck said:
    3. Can we use SYSREF in a deterministic manner to align the clock outputs?


    Take a look at this attachment, perhaps this will help you do what you want, depending on your needs I would recommend using CLKin0 over SYNC as illustrated here, but depending on the needs.  Note in this case the particular edge was not a concern, just that it was aligned when turning on/off.

    Sort of an alternate use of the JESD204B divider for SYNC alignment.

    LMK04828 Reclocked SYNC for LM97600.pdf

    But to do synchronization for different devices, you will still run into the issue of SYNCing the SYSREF divider together.  To achieve this I suggest what I recommend below about using 0-delay.  Let me know how this may work for you?  Part of the issue here is that the Clock Distribution Path frequency is so high, SYNCing any divider to the same edge will be tricky - there will be some variation related to the VCO frequency which you may or may not accept.  Another possibility is that VCO1 of LMK04821 (2.9 GHz VCO) has a VCO divider which could be used to reduce the clock distribution path frequency which may help, but again - I don't have the setup/hold times on this.

    Simplest option is the 0-delay stuff below.  Let me know what you think.

    Steven Naboicheck said:
    4. What is the sampling rate of the SYNC signal for the LMK04828B and do you have a better timing diagram for this process?


    I'm not sure I fully follow this comment.  The SYSREF divider is programmable from 8 to 8191.

    ---


    For synching multiple devices together.  One simple closed loop technique is to use LMK04826 in dual loop nested 0-delay mode.  Suppose you supply a 10 MHz reference to all LMK04826 devices for CLKin.  Then PLL1 uses 100 MHz VCXO to provide a reference to PLL2 which locks to 2500 MHz.  Then program SYSREF divider for 10 MHz, and feed that back to PLL1 N input (the 0-delay feedback path).  When you perform a SYNC on each device, all the output phases of each device will align with the SYSREF divider.  Because this same 10 MHz is fanned out to all LMK clock inputs and is phased aligned with all 10 MHz signals from SYSREF divider, all the clock signals will be aligned.



    73,

    Timothy