Hi,
Recently we purchased the LMK040xx Evaluation Board, and there is some issue to make this board work.
The schematics in the LMK040xx Evaluation Board is not readable.
Can I get the schematics for the above board.
Thanks,
Charles
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Hi,
Recently we purchased the LMK040xx Evaluation Board, and there is some issue to make this board work.
The schematics in the LMK040xx Evaluation Board is not readable.
Can I get the schematics for the above board.
Thanks,
Charles
Hi Charles,
Sorry for the inconvenience. I've attached the schematics to this post, and will get the users guide updated. Please let me know if anything else. Thanks!
Regards,
Brian Wang
Hi Brian,
When the divider is changed on PLL2, I could see a change in the output clock.
Yes I am using LMK04033B and connected external 26MHz directly to the OSCin on the PCB (Other parts on the OSC line are disconnected).
I do not see the D1 LED on, whe the "PLL2 DLD Active High" is loaded.
I am not able to file files from this forum. Please let me know how to attach the file.
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In another context; This is regarding the actual problem that we are seeing in our system.we are using the the LMK04033B chip on our board.
We are able to program the correct frequency 17.92MHz. But we see a difference in the clk output (more jitter) during reprogramming. Does the way the programming is done can affect the Clk output in terms of jitter. We are getting the correct frequency after reprogramming.
I observed from the uwire interface (Clk,data and latch enable) on the eval board. The clock is around 64KHz, and clock to clock delay (register to next register programming) is around 2.4ms. But where as on our board, we have clock frequency of 100KHz and clock to clock delay (register to next register programming) is 12us. Can this cause any problem for jitter. Also I observe that for changing the output frequency only R2 register changes on the eval board.
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Thanks & Regards,
Charles
Hi Charles,
If you are able to get the correct frequency after reprogramming, your programming methodology should be correct. As you've observed the Clk, data, latch enable are the three pins used to program the device. Just make sure you don't violate the timing requirements in the microwire interface timing section (bottom of page 18 and top of page 19 in datasheet). Once you are in lock, the three signals clk/data/LE are held at low state, thus any changes including reprogramming or unintended toggling of these lines can introduce phase degradation and as a result more jitter.
(for attachments, switch to "use rich formatting", bottom right of the reply box)
Also, jitter depends a lot on your loop configurations. Since you are configuring your system and loop characteristics, here is a simulation tool that can greatly help you: http://www.ti.com/tool/clockdesigntool
With the Clock Design Tool you can select the device you are using, configure the PLL block by block while observing the loop bandwidth, phase noise, and jitter numbers. Here is an example screenshot of your configuration I set in the tool as well as a screenshot of clicking on the simulate button at CLKout0 to see phase noise contribution and jitter. Let me know if any further questions. Thanks!
Hi Charles,
The lookup table is basically an analytical calculation using the OSCin, R, N values, converting to binary and entering into corresponding registers specified by datasheet. Did you want something more excel-based, or displaying formulas? Thanks!
Regards,
Brian Wang
Hi Charles,
Here is an example how to figure out how to get your output frequencies using the Clock Design Tool, then configuring in Codeloader. Please let me know if it is unclear. Thanks!