Hi,
We are using four CDCM6208 for LVDS clocking input to Keystone-II devices. We have configured the Pin mode of CDCM6208 as per table:10 to get the desired output clock.
As per table:10 ,all our desired output required 25MHz LVDS at PRI_REF or 25MHz crystal at SEC_REF . Due to real estate issue,we are using 3.3V CMOS single ended input clock(P/N:KC2520B25.0000C2GE00) through buffer(P/N:NB2305AI1HDR2G) connected to SEC_REFP pin of all four CDCM6208.
I have attached the schematics. Need suggestions on our design.
