CDCM6208V1RGZT Clock Generation Schematic. Kindly review the attached schematics and reply your suggestion soon.

Hi Asarudeen,

Two major comments here: refer to this E2E post about using a LVDS buffer instead of a LVCMOS buffer: e2e.ti.com/.../412365

Also, please follow the recommended power supply decoupling scheme as found in the CDCM6208 DS. VDDVCO and VDDPLL2 can be tied together and decoupled with a 0.1uF and 100pF capacitors. This net can then be tied with a ferrite bead to VDDPLL1 which is additionally decoupled with decade capacitors from 10 uF, 1 uF, and 0.1uF tied to 3.3V.

DVDD requires additional decoupling in the form of a 0.1uF and 1uF and can be connect to 3.3V.

Gabe

Additionally, note that the outputs need to be AC coupled and possibly rebiased on the Rx devices. This is due to the CML output structure of the CDCM6208.