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Synchronizing multiple CDCE62005 Outputs

LeonardEllis
Guru 71526 points
Other Parts Discussed in Thread: CDCE62005

We have two boards, each with a CDCE62005, fed by a single 250MHz CLK, and we want to ensure the outputs of both CDCE62005's are in sync.  It seems this question has come up before in this post: https://e2e.ti.com/support/clocks/f/48/t/48547 , however, it is unanswered. 

If we use the CDCE62005 basically as a buffer, with the output at 250MHz, how does the PLL lock time affect this synchronization?  And the propagation delay that is specified.  Will either the PLL lock time or the Propagation Delay change each time the board is powered-ON, or will these times remain constant? 

Finally, the first post referenced suggested Fig 32 page 54 in the datasheet, but I do not see this reference in the datasheet - has it been deleted or moved?

~Leonard 

 

  • 0
    TI__Expert 4400 points

    Hi Leonard, you can use the SYNCN pin to synchronize the outputs among the 2 CDCE62005. The delay of outputs from the SYNC low-to-high pulse is explained in pages 38 and 39. It is best to select the prescaler clock for the output MUX to minimize the uncertainty.

  • 0
    Intellectual 450 points
    Hi, the question was coming from me at first, but I dig a little bit into that and now we thing that using the sync pin isn't very doable for us as we are using the reference clock to clock another board so we want the CDCE to add the lowest phase delay as possible.

    BAsically, what we want to do is that we want to feed a 250MHz clock to 3 different cards, 2 with a CDCE62005RGZ and another card with the 250MHz direct connect to ADC/DAC. We want those cards not necessarily perfectly synchronized, but at least knowing if the system will have a fixed phase-delay from power up to another. What I understand is that we can't bypass completely the CDCE PLL, so we wonder what can be the min and max phase delay from one power up to another if we have a ratio of 1 (250MHz in 250MHz out). I guess mainly the PLL lock time that will differ from time to time, but is there a way to narrow the phase delay to a minimum difference from power up to another?
  • 0 in reply to Madhu Balasubramanian
    Intellectual 450 points
    Hi Madhu, for the case of only 2 CDCE62005, by using the prescaler as you said, does the phase delay between output and input will be completly random from a power-up to another or it will be around the same value each time?
    Thanks!
  • 0 in reply to David Lacasse
    TI__Expert 4400 points
    Hi David,

    the only way to minimize the uncertainty would be using the SYNCN pin and the max uncertainty is the inverse of the prescaler clock.