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Do I need a transmission line at 40MHz? What is the capacitance of the trace?



Question:

We need to route a clock signal over a trace lenght of 6"-8" to high-speed (~40MHz) IO buffers. Since we don’t often deal with anything of this high speed, we are hoping to get a few recommendations on how to accomplish this. If a board designer were to stretch a clock line about 8 inches across a board, do you guys have any feel for the parasitics that would be generated? I’m assuming a pretty narrow trace? Can we simply calculate the capacitance of the trace to look at the clock driver output load or do we need to design matching impedance lines? Do you have a quick recommendation?

 

  • Answer from TI:

    Hi, you can not simply look at a transmission line as a capacitor UNLESS the trace electrical delay is shorter than 1/4th of the signal rise time (which is not true for 40MHz over 6").

    For a clock signal (trapezideal signal) of higher frequency, the 6" trace becomes a transmission line with distributed capacitance over the length of the transmission line. All capacitive components are separated from each other with inductive components over the trace length. So while it's possible to calculate the capacitance of a trace (function of trace width and height over the GND plane) you would get the wrong results by simply checking if an output can drive a certain capacitance. The result would only be true in DC, not at 40MHz.

    What I recommend is very simple to do and will get you much better results. Check the output impedance of the driver, and match it with a series resistor such that the output impedance + series resitor equal the transmission line impedance. Most transmission lines are designed for 50

    Ω transmission line impedance. A standard LVCMOS output has an impedance of anywhere from 10Ω το 45Ω, so you would need a series restor between 5Ω to 40Ω to get to 50Ω

    total output impedance.

     

    7725.CH_1_basic_v5.pdf

    Good luck! Fritz