Question:
We need to route a clock signal over a trace lenght of 6"-8" to high-speed (~40MHz) IO buffers. Since we don’t often deal with anything of this high speed, we are hoping to get a few recommendations on how to accomplish this. If a board designer were to stretch a clock line about 8 inches across a board, do you guys have any feel for the parasitics that would be generated? I’m assuming a pretty narrow trace? Can we simply calculate the capacitance of the trace to look at the clock driver output load or do we need to design matching impedance lines? Do you have a quick recommendation?