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LMX2581: How to step the frequency easily in 0-DELAY mode with TICS-Pro

Part Number: LMX2581
Other Parts Discussed in Thread: , CODELOADER, USB2ANY, LMX2594, LMX2572

Hello,
I have a question about stepping the frequency in 0-Delay mode using TICS-Pro.  I am operating it with the following setup:

Device;LMX2581
Evaluation board: LMX2581EVM in original configuration with internal VCO. 
Software; Codeloader program version 4.20.02, Part file version 2014-11-09
Reference; 100MHz
Windows 7 SP1 64 bit
Connected with USB2ANY
Register map (for 0-Delay mode):
R15 0x021FE80F
R13 0x4082410D
R10 0x210050CA
R9 0x03C7C039
R8 0x207DDBF8
R7 0x00082317
R6 0x000004C6
R5 0x0030AC05
R4 0x00000004
R3 0x2004F3E3
R2 0x0C000642
R1 0xC2002021
R0 0x700C0000

When I step the frequency using the N divider (PLL_N) from 600MHz to 650MHz in 0 Delay mode in TICS-Pro,  I find the output frequency doesn’t step to 650MHz as expected but only to 602.597MHz. I am stepping N from 12 to 13, and have the divider set at 4.  

I discovered the only way I can get an accurate step in frequency I need to follow the following procedure:
- Reprogram the synthesiser with saved non 0-Delay mode register map.
- Change the frequency to what I want in non 0-Delay mode.
- Follow the instructions in 8.3.10 in the LMX2581 datasheet to get to 0-Delay mode again.
 

Are we meant to be able to step it in 0-Delay mode like I first tried?  Is there an easier way to get an accurate step?  Or is there something I was doing wrong with the software?
Many thanks!

  • The software I am using is not Codeloader as I have shown in the setup above

    It's TICS-Pro version 1.6.5.0 Build date 16 Aug 17. Part version 2016-03-23.

  • Northley,

    The datasheet procedure that you show gives answer to your question. VCO calibration does not work in 0-Delay mode. So the only way that stepping is possible is if the step is small enough (say 10 MHz or so) so that the VCO does not need or try to re-calibrate. So if yo uset FCAL_EN=0 in 0-Delay mode and have a PLL in lock, you could step it in 1 MHz steps, but if the VCO gets too far away, then it crashes into the end of the frequency band.

    Regards,
    Dean
  • Thanks Dean, I will try stepping it by under 1MHz steps and setting FCAL_EN=0 steps and see if that works,
  • Northley,
    OK. Sounds good. Just to clarify, you should be able to do 1 MHz steps, but you can't deviate too far from the frequency that you calibrated at.
    Regards,
    Dean
  • Hey Dean,
    I have been experimenting with stepping the frequency in 0-Delay mode in 1MHz steps as you mentioned above and with frequency calibration off (I assume FCAL_EN=0 is the same as NO_FCAL=1) . I have it set at 600MHz with a divider of 4 (so VCO frequency of 2400MHz) and 50MHz PFD frequency. It manages to step accurately from 600-603MHz and then it seems to hit its limit. This is only a small part of a PFD cycle of 50MHz.

    This means i can only set the frequency in 0-Delay mode to each integer boundary frequency with 3MHz above that (ie 600-603MHz, 650-653MHz etc). We were hoping to be able to use the whole 50MHz cycle in fractional mode and 0-Delay mode.

    Is there any way I can use the PLL in 0-Delay mode over the whole PFD (50MHz in this case) cycle? Is there any way to recalibrate while you are in 0-Delay mode?

    Many Thanks,
    Helen
  • Helen,
    What you are seeing is expected. You lock the PLL and you move the frequency, but when the VCO frequency gets about more than 12 MHz from where it calibrates, it needs to re-calibrate. The LMX2581 divides the entire frequency range into 4 cores with 256 different frequency bands, so this would be the boundary of that frequency band.

    Calibration would be necessary if you want to move your output by 50 MHz (That's 200 MHz at the VCO frequency). Unfortnuately, the only way to recalibrate is to switch back to normal mode (non 0-delay) and switch it back to 0 delay mode.

    There is a way to force a particular VCO core and Capcode and then force this value to bypass the calibration by using VCO_CAPCODE_MAN, but these settings would change for every part and every temperature.

    Regards,
    Dean
  • Hello Dean,
    Thanks for your reply,
    Just to clarify, please let me know if I haven't understood fully;

    It looks like it wouldn't be possible to use the whole PFD cycle in 0-Delay mode without forcing a particular VCO core and capcode as mentioned in the last paragraph above. Which would mean an un-calibrated and hence inaccurate output frequency.

    From the steps needed to set the PLL to 0-Delay mode, in step 1 you need N to be divisible by the divider. This means that you can only change to 0-Delay mode at each integer boundary. Supposing I needed 620MHz output which is 20MHz away from the integer boundary. To go back to normal mode then back to 0-Delay mode i could only set to 600 or 650MHz, but not 620MHz. 620MHz would require the N value to be non divisible by the divider value. And hence there would be no way of setting it to 620MHz in 0-Delay mode except by the forcing VCO core and Capcode you mentioned above. But it appears it would not be calibrated and hence not accurate in frequency.

    It appears this particular chip may not be able to do what we want but i'm interested to see if you have others that will.
    What we need is:

    Fpfd=50MHz (no divider used in the reference path)
    Fvco=2200-3000MHz
    Fout=550-750MHz
    Divider=4 (inside the loop)

    Would you suggest anything else?
    Many thanks for your help,
    Helen
  • Helen,

    With the LMX2581, you can 0-Delay mode, but it is more limited.

    You might want to consider the LMX2594 that has a true 0-delay mode that you can step easily likely you want.

    Also, consider the LMX2572, which is a lower frequency version of the LMX2594.  The LMX2572 is not released, but will be this year and the datasheet is on the web.

    Regards,

    Dean

  • Hello Dean,

    Thanks for your help!  it is much appreciated,

    my colleague and I discovered a way that we can get the LMX2581 to do what we want.  I thought i'd post it up here incase it is helpful for anyone.

    It was discovered that any frequency in between the 50MHz PFD frequency cycle can be obtained by setting the Fpfd frequency smaller (say 1MHz) temporarily.  This means you can choose any integer frequency while the Fpfd is 1MHz, and still step it to what is wanted before the VCO becomes uncalibrated.   For some reason when the Fpfd is flicked back to 50MHz, the chip stays in O-Delay mode and also fractional mode.

    The method used is as below (cumbersome but it works)

    • In normal mode set Fpfd=1MHz and Fout to whatever integer frequency is closest to that wanted.
    • Change to 0-Delay mode
    • Change Fpfd to 50Mhz
    • Step the Fout to that frequency wanted.

    Example: Setting to 620.45MHz: (which would be impossible with Fpfd always at 50MHz)

    • In normal mode set Fpfd=1MHz and Fout=620MHz. (needs to be 620MHz as PLL cant be changed to 0-Delay mode in fractional mode).
    • Change to 0-Delay mode
    • Change Fpfd to 50Mhz
    • Step PLL_NUM until Fout=620.45MHz

    Cheers,

    Helen